{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:45:00Z","timestamp":1759146300689},"reference-count":14,"publisher":"World Scientific Pub Co Pte Lt","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2014,6]]},"abstract":"<jats:p> In this study, a multistage fault-tolerant (MSFT) scheme for two fixed-width array multipliers is proposed. To tolerate the fault that occurs in an integrated circuit, an architecture by using three redundant triple module redundancy (TMR) processing elements (PEs) (TMR-PE) is proposed. The proposed Type-I MSFT multipliers divide the array multiplier into multiple stages, and implement a single PE by considering multiple computation cycles to achieve a low area design. Thus, the MSFT multiplier employs the TMR-PEs to achieve a low-cost fault-tolerant design. The TMR-PEs were designed using compressors with multiple operands, such as 4-2 compressors or other compressors with additional operands, to reduce the number of computation cycles and expedite the execution process. To improve the fault-correction capability, Type-II MSFT multipliers that follow the multistage structure, which was designed as a TMR technique, were proposed. Because of implementation using a 0.18-\u03bcm CMOS process, the long word-length MSFT multiplier saves a substantial amount of the circuit area. The proposed 64 \u00d7 64 Type-I MSFT multiplier has only 13% of the circuit area and 3% of the delay overhead of the original multiplier. Based on the measurements of the area-delay product (AT) metric, the value of the 64 \u00d7 64 Type-I MSFT multiplier is only 0.21-fold of the value of the original multiplier. Regarding the fault-correction capability, the 64 \u00d7 64 Type-II MSFT multiplier achieves an area-delay-fault efficiency (ATF) that is 11-fold of the value of the original TMR multiplier. <\/jats:p>","DOI":"10.1142\/s0218126614500741","type":"journal-article","created":{"date-parts":[[2014,2,11]],"date-time":"2014-02-11T01:50:46Z","timestamp":1392083446000},"page":"1450074","source":"Crossref","is-referenced-by-count":4,"title":["A MULTI-STAGE FAULT-TOLERANT MULTIPLIER WITH TRIPLE MODULE REDUNDANCY (TMR) TECHNIQUE"],"prefix":"10.1142","volume":"23","author":[{"given":"YUAN-HO","family":"CHEN","sequence":"first","affiliation":[{"name":"Department of Information and Computer Engineering, Chung Yuan Christian University, Taoyuan 320, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"CHIH-WEN","family":"LU","sequence":"additional","affiliation":[{"name":"Department of Engineering and System Science, National Tsing Hua University, Hsinchu 300, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"SHIAN-SHING","family":"SHYU","sequence":"additional","affiliation":[{"name":"Institute of Nuclear Energy Research, Atomic Energy Council, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"CHUNG-LIN","family":"LEE","sequence":"additional","affiliation":[{"name":"Institute of Nuclear Energy Research, Atomic Energy Council, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"TING-CHIA","family":"OU","sequence":"additional","affiliation":[{"name":"Institute of Nuclear Energy Research, Atomic Energy Council, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2014,5,8]]},"reference":[{"key":"rf1","volume-title":"VLSI Digital Signal Processing Systems: Design and Implementation","author":"Parhi K. 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