{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,12,31]],"date-time":"2022-12-31T07:17:09Z","timestamp":1672471029083},"reference-count":19,"publisher":"World Scientific Pub Co Pte Lt","issue":"06","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2014,7]]},"abstract":"<jats:p> A new two-stage method of finite state machines (FSMs) synthesis for PAL-based complex programmable logic devices (CPLD) is proposed. It is based on both the wide fan-in of PAL cells and existence of the classes of pseudoequivalent states of Moore FSM. The first step targets decreasing for the number of PAL cells used for implementing the block of input memory functions. The second step targets decreasing for the number of PAL cells in the block of microoperations. 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