{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T08:09:43Z","timestamp":1771488583013,"version":"3.50.1"},"reference-count":18,"publisher":"World Scientific Pub Co Pte Lt","issue":"08","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2014,9]]},"abstract":"<jats:p> In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low. <\/jats:p>","DOI":"10.1142\/s0218126614501084","type":"journal-article","created":{"date-parts":[[2014,5,27]],"date-time":"2014-05-27T23:11:19Z","timestamp":1401232279000},"page":"1450108","source":"Crossref","is-referenced-by-count":18,"title":["COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS"],"prefix":"10.1142","volume":"23","author":[{"given":"VANDANA","family":"NIRANJAN","sequence":"first","affiliation":[{"name":"Department of Electronics &amp; Communication Engineering, Indira Gandhi Delhi Technical University for Women, Kashmere Gate, New Delhi 110006, India"}]},{"given":"ASHWANI","family":"KUMAR","sequence":"additional","affiliation":[{"name":"Department of Electronics &amp; Communication Engineering, Indira Gandhi Delhi Technical University for Women, Kashmere Gate, New Delhi 110006, India"}]},{"given":"SHAIL BALA","family":"JAIN","sequence":"additional","affiliation":[{"name":"Department of Electronics &amp; Communication Engineering, Indira Gandhi Delhi Technical University for Women, Kashmere Gate, New Delhi 110006, India"}]}],"member":"219","published-online":{"date-parts":[[2014,6,18]]},"reference":[{"key":"rf1","doi-asserted-by":"publisher","DOI":"10.1023\/B:ALOG.0000016641.83563.96"},{"key":"rf3","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-69954-7"},{"key":"rf4","doi-asserted-by":"publisher","DOI":"10.1109\/4.309905"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1080\/00207210412331314196"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1080\/00207211003646928"},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1007\/0-387-25747-0_4"},{"key":"rf9","doi-asserted-by":"publisher","DOI":"10.1109\/4.735525"},{"key":"rf10","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-012-0001-y"},{"key":"rf11","doi-asserted-by":"publisher","DOI":"10.1049\/el.2013.0554"},{"key":"rf14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2192458"},{"key":"rf15","first-page":"415","volume":"22","author":"Khateb F.","year":"2013","journal-title":"Radioengineering"},{"key":"rf16","first-page":"89","volume":"6","author":"Niranjan V.","year":"2011","journal-title":"J. Active Passive Electronics Dev."},{"key":"rf18","first-page":"161","volume":"83","author":"Takamiya M.","year":"2000","journal-title":"IEICE Trans. Electronics Dev."},{"key":"rf19","doi-asserted-by":"publisher","DOI":"10.1109\/16.556151"},{"key":"rf20","volume-title":"Operation and Modeling of the MOS Transistor","author":"Tsividi Y. P.","year":"1987"},{"key":"rf22","doi-asserted-by":"publisher","DOI":"10.1016\/S0038-1101(03)00297-1"},{"key":"rf23","volume-title":"Microelectronic Circuits","author":"Sedra A. S.","year":"2006"},{"key":"rf24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.848021"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126614501084","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T18:21:20Z","timestamp":1565115680000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126614501084"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6,18]]},"references-count":18,"journal-issue":{"issue":"08","published-online":{"date-parts":[[2014,6,18]]},"published-print":{"date-parts":[[2014,9]]}},"alternative-id":["10.1142\/S0218126614501084"],"URL":"https:\/\/doi.org\/10.1142\/s0218126614501084","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,6,18]]}}}