{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T16:41:55Z","timestamp":1648917715267},"reference-count":8,"publisher":"World Scientific Pub Co Pte Lt","issue":"01","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2015,1]]},"abstract":"<jats:p> It is well known that multiplierless finite impulse response (FIR) filters in multiple-stage cascade form can achieve lower hardware cost and lower coefficient sensitivity than that of single stage design. In this work, a novel algorithm is proposed for the design of multiplierless multiple-stage cascaded FIR filters. Unlike to the conventional algorithms in which the number of stages is fixed and usually is fixed to two, the number of stage in the proposed algorithm is automatically determined. The design examples show that the proposed algorithm significantly outperforms the best existing algorithm in terms of hardware cost and the design time is also saved. <\/jats:p>","DOI":"10.1142\/s0218126615500115","type":"journal-article","created":{"date-parts":[[2014,9,24]],"date-time":"2014-09-24T08:56:02Z","timestamp":1411548962000},"page":"1550011","source":"Crossref","is-referenced-by-count":0,"title":["Multiplierless Multiple-Stage Cascaded FIR Filter Design"],"prefix":"10.1142","volume":"24","author":[{"given":"Wenbin","family":"Ye","sequence":"first","affiliation":[{"name":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2014,11,10]]},"reference":[{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1109\/82.539000"},{"key":"rf4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.904599"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-009-9114-7"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2268551"},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1109\/29.9010"},{"key":"rf10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2143250"},{"key":"rf11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2055290"},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1983.1164085"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126615500115","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T20:16:56Z","timestamp":1565122616000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126615500115"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11,10]]},"references-count":8,"journal-issue":{"issue":"01","published-online":{"date-parts":[[2014,11,10]]},"published-print":{"date-parts":[[2015,1]]}},"alternative-id":["10.1142\/S0218126615500115"],"URL":"https:\/\/doi.org\/10.1142\/s0218126615500115","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,11,10]]}}}