{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T23:12:12Z","timestamp":1648768332140},"reference-count":8,"publisher":"World Scientific Pub Co Pte Lt","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2015,3]]},"abstract":"<jats:p> This paper, focus on synthesis design of a \u0394\u2013\u03a3 digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio DAC. The features of the design are high-precision, fast processing and low-cost. The related work is done with the MATLAB &amp; QUARTUS II simulators. <\/jats:p>","DOI":"10.1142\/s0218126615500371","type":"journal-article","created":{"date-parts":[[2014,12,10]],"date-time":"2014-12-10T08:59:36Z","timestamp":1418201976000},"page":"1550037","source":"Crossref","is-referenced-by-count":2,"title":["FPGA-Based Design \u0394\u2013\u03a3 Audio D\/A Converter with a Resolution Clock Generator Enhancement Circuit"],"prefix":"10.1142","volume":"24","author":[{"given":"Noura Ben","family":"Ameur","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, National Engineering School, Soukra Street, Sfax 3038, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nouri","family":"Masmoudi","sequence":"additional","affiliation":[{"name":"Electronics and Communication Research Group, Laboratory of Electronics and Information Technology, Soukra Street, Sfax 3038, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mourad","family":"Loulou","sequence":"additional","affiliation":[{"name":"Analogue, Mixed Mode and RF Design Group, Laboratory of Electronics and Information Technology, Sour Street, Sfax 3038, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2015,2,10]]},"reference":[{"key":"rf1","volume-title":"Oversampling Delta-Sigma Data Converters","author":"Candy J. C.","year":"1992"},{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1109\/9780470544358"},{"key":"rf5","first-page":"1","volume":"10939278","author":"Kim S.-H.","year":"2009","journal-title":"IEEE Power Electron. Appl."},{"key":"rf6","volume":"1","author":"Maity S. Kr.","year":"2012","journal-title":"Int. J. Soft Comput. Eng."},{"key":"rf8","first-page":"2249","volume":"11","author":"Islam S. Md. Rabiul","year":"2011","journal-title":"J. Res. Eng. Electr. Electron. Eng."},{"key":"rf10","first-page":"222","volume":"2","author":"Ameur N. Ben","year":"2008","journal-title":"Int. J. Electr. Circuits Syst."},{"key":"rf19","first-page":"328","author":"Note S.","year":"1992","journal-title":"IEEE Comput.-Aided Design Integr. Circuits Syst."},{"key":"rf21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887923"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126615500371","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T04:51:42Z","timestamp":1565153502000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126615500371"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2,10]]},"references-count":8,"journal-issue":{"issue":"03","published-online":{"date-parts":[[2015,2,10]]},"published-print":{"date-parts":[[2015,3]]}},"alternative-id":["10.1142\/S0218126615500371"],"URL":"https:\/\/doi.org\/10.1142\/s0218126615500371","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,2,10]]}}}