{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:16:59Z","timestamp":1758892619243},"reference-count":21,"publisher":"World Scientific Pub Co Pte Lt","issue":"04","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2015,4]]},"abstract":"<jats:p> The signals in reality are sparse signal where a few numbers of samples are non-zero. So, a compression technique must be applied to reduce the overhead of processing, storing, and transmission. Blocking compressive sampling matching pursuit (BCoSaMP) algorithm is a recursive algorithm which provides an accurate reconstruction of sparse signal from a small number of noisy samples. It doesn't assume that the noise is Gaussian or bounded but it uses information about the noise magnitude for stopping criterion. However, BCoSaMP is a computationally intensive algorithm. So, BCoSaMP algorithm has been implemented on both field-programmable gate array (FPGA) and graphic processing units (GPU) by exploiting parallel and pipelining approaches. A new software tool called radar signal processing tool (RSPT) is also presented. It allows the designer to auto-generate fully optimized VHDL representation of BCoSaMP by specifying many user input parameters through graphical user interface (GUI). Moreover, it provides the designer a feedback on various performance parameters. This offer the designer the ability to make any adjustments to the BCoSaMP component until gets the desired performance of the overall system-on-chip (SoC). Our simulation results indicate that the achieved speed-up of FPGA and GPU over the sequential one is improved by up to 14 and 10.7, respectively. <\/jats:p>","DOI":"10.1142\/s0218126615500553","type":"journal-article","created":{"date-parts":[[2015,1,23]],"date-time":"2015-01-23T08:01:11Z","timestamp":1422000071000},"page":"1550055","source":"Crossref","is-referenced-by-count":4,"title":["Reconfigurable FPGA\/GPU-Based Architecture of Block Compressive Sampling Matching Pursuit Algorithm"],"prefix":"10.1142","volume":"24","author":[{"given":"Amin","family":"Jarrah","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering &amp; Computer Science, The University of Toledo, 2801 W. Bancroft, Toledo, OH 43606, USA"}]},{"given":"Mohsin M.","family":"Jamali","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering &amp; Computer Science, The University of Toledo, 2801 W. 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