{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,12]],"date-time":"2024-07-12T22:00:52Z","timestamp":1720821652551},"reference-count":4,"publisher":"World Scientific Pub Co Pte Lt","issue":"07","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2015,8]]},"abstract":"<jats:p> This work is focused on the problem of designing efficient reconfigurable multiplexer banks for RAM-based implementations of reconfigurable state machines. We propose a new architecture (called combination-based reconfigurable multiplexer bank, CRMUX) that use multiplexers simpler than that of the state-of-the-art architecture (called variation-based reconfigurable multiplexer bank, VRMUX). The performance (in terms of speed, area and reconfiguration cost) of both architectures is compared. Experimental results from MCNC finite state machine (FSM) benchmarks show that CRMUX is faster and more area-efficient than VRMUX. The reconfiguration cost of both multiplexer banks is studied using a behavioral model of a reconfigurable state machine. The results show that the reconfiguration cost of CRMUX is lower than that of VRMUX in most cases. <\/jats:p>","DOI":"10.1142\/s0218126615501017","type":"journal-article","created":{"date-parts":[[2015,5,21]],"date-time":"2015-05-21T23:07:40Z","timestamp":1432249660000},"page":"1550101","source":"Crossref","is-referenced-by-count":7,"title":["High-Speed and Area-Efficient Reconfigurable Multiplexer Bank for RAM-Based Finite State Machine Implementations"],"prefix":"10.1142","volume":"24","author":[{"given":"Raouf","family":"Senhadji-Navaro","sequence":"first","affiliation":[{"name":"Computer Architecture and Technology Department, Higher Technical School of Computer Engineering, University of Seville, Avda. Reina Mercedes s\/n, Seville 41012, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ignacio","family":"Garcia-Vargas","sequence":"additional","affiliation":[{"name":"Computer Architecture and Technology Department, Higher Technical School of Computer Engineering, University of Seville, Avda. Reina Mercedes s\/n, Seville 41012, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2015,6,17]]},"reference":[{"key":"rf1","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(02)00067-X"},{"key":"rf4","doi-asserted-by":"publisher","DOI":"10.1016\/S0166-218X(02)00457-2"},{"key":"rf7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"rf14","doi-asserted-by":"publisher","DOI":"10.1049\/el:20046007"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126615501017","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T14:11:00Z","timestamp":1565100660000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126615501017"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6,17]]},"references-count":4,"journal-issue":{"issue":"07","published-online":{"date-parts":[[2015,6,17]]},"published-print":{"date-parts":[[2015,8]]}},"alternative-id":["10.1142\/S0218126615501017"],"URL":"https:\/\/doi.org\/10.1142\/s0218126615501017","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,6,17]]}}}