{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T22:56:29Z","timestamp":1649112989403},"reference-count":7,"publisher":"World Scientific Pub Co Pte Lt","issue":"07","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2015,8]]},"abstract":"<jats:p> In the case of the reconfigurable module, the popular logic function implementation is based on the look-up-table (LUT) structure. Once a Boolean network of single-rail n-variable node functions is transformed into a dual-rail one, each variable is represented as two literals: x and its inversion x<jats:sup>\u2032<\/jats:sup> and implemented using two separate signals. As a result, (2n + 1)-input LUTs are required for mapping node functions. To reduce the capacity of required LUTs, the literal decomposition method is proposed. It is applied to implement a dual-rail node function using k-input LUTs, n &lt; k &lt; (2n + 1). The literal decomposition over the chosen variable is based on creating two clusters where one of the clusters contains minterms with the literal x of the chosen variable, the other one contains minterms with the literal x<jats:sup>\u2032<\/jats:sup>. Functions created based on each cluster minterms depend on less literals number than the original one. The procedure is repeated until the required number of literals is reached. The literal decomposition is used as a post processing of the conventional decomposition procedure. Depending on the logic architecture, different implementations are considered and discussed. The implementation complexity (in terms of LUTs number) for different values n, k is given. <\/jats:p>","DOI":"10.1142\/s0218126615501108","type":"journal-article","created":{"date-parts":[[2015,6,9]],"date-time":"2015-06-09T23:17:16Z","timestamp":1433891836000},"page":"1550110","source":"Crossref","is-referenced-by-count":0,"title":["Literal Decomposition for LUT-Oriented Asynchronous Dual-Rail Logic Synthesis"],"prefix":"10.1142","volume":"24","author":[{"given":"Igor","family":"Lemberski","sequence":"first","affiliation":[{"name":"Information Technology Department, Baltic International Academy, Lomonosova 4, Riga LV-1019, Latvia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2015,6,17]]},"reference":[{"key":"rf3","volume-title":"Asynchronous Sequential Switching Circuits","author":"Unger S. H.","year":"1969"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1109\/43.402498"},{"key":"rf9","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139166980"},{"key":"rf11","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3385-3"},{"key":"rf14","doi-asserted-by":"crossref","unstructured":"S. C.\u00a0Smith and J.\u00a0Di, Designing Asynchronous Circuits using NULL Convention Logic (NCL) (Morgan & Claypool, 2009)\u00a0p. 96.","DOI":"10.2200\/S00202ED1V01Y200907DCS023"},{"key":"rf16","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2013.02.002"},{"key":"rf18","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.0242"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126615501108","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T14:11:25Z","timestamp":1565100685000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126615501108"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6,17]]},"references-count":7,"journal-issue":{"issue":"07","published-online":{"date-parts":[[2015,6,17]]},"published-print":{"date-parts":[[2015,8]]}},"alternative-id":["10.1142\/S0218126615501108"],"URL":"https:\/\/doi.org\/10.1142\/s0218126615501108","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,6,17]]}}}