{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T02:37:40Z","timestamp":1761964660348},"reference-count":17,"publisher":"World Scientific Pub Co Pte Lt","issue":"08","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2015,9]]},"abstract":"<jats:p> This paper presents a new high-performance and low-power single-supply voltage level converter (SSLC) and a new carry save array multiplier based on clustered-voltage scaling (CVS) technique for ultra-low-power applications. The multiplier operates with low and high supply voltage (V<jats:sub> DDL <\/jats:sub>, V<jats:sub> DDH <\/jats:sub>) and at its end stage, the proposed low-power SSLC is utilized to prevent static power dissipation at the next stage working with V<jats:sub> DDH <\/jats:sub> and to enhance the output driving capability. In the proposed SSLC, dynamically-controlled source-body voltage, reduced drain induced barrier lowering (DIBL) effect and diode-connected transistor with body-biasing have been utilized properly in order to reduce the power consumption significantly without considerable speed degradation. The results of the simulations conducted using Cadence with standard 90-nm CMOS technology demonstrate the superiority of the proposed multiplier utilizing the proposed LC in terms of static and total power consumptions as well as power-delay product (PDP) as compared to the multipliers utilizing the previous level converters (LCs) and the single supply multiplier. It is worth mentioning that the static power, total power and PDP of the proposed low-power multiplier are on average 75%, 73% and 16%, respectively lower than the single-supply multiplier. <\/jats:p>","DOI":"10.1142\/s0218126615501248","type":"journal-article","created":{"date-parts":[[2015,7,2]],"date-time":"2015-07-02T00:03:39Z","timestamp":1435795419000},"page":"1550124","source":"Crossref","is-referenced-by-count":10,"title":["A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter"],"prefix":"10.1142","volume":"24","author":[{"given":"Majid","family":"Moghaddam","sequence":"first","affiliation":[{"name":"Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Evin 1983963113, Tehran, Iran"},{"name":"Microelectronics Lab, Shahid Beheshti University, G.C., Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohammad Hossein","family":"Moaiyeri","sequence":"additional","affiliation":[{"name":"Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Evin 1983963113, Tehran, Iran"},{"name":"Microelectronics Lab, Shahid Beheshti University, G.C., Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohammad","family":"Eshghi","sequence":"additional","affiliation":[{"name":"Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Evin 1983963113, Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ali","family":"Jalali","sequence":"additional","affiliation":[{"name":"Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Evin 1983963113, Tehran, Iran"},{"name":"Microelectronics Lab, Shahid Beheshti University, G.C., Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2015,8,12]]},"reference":[{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2014.1293"},{"key":"rf3","volume-title":"Sub-Threshold Design for Ultra Low-Power Systems","author":"Calhoun W. B. H.","year":"2006"},{"key":"rf4","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126611007517"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2013.1251"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1080\/00207211003646944"},{"key":"rf7","first-page":"14","volume":"69","author":"Moghaddam M.","year":"2013","journal-title":"Int. J. Comput. Appl."},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-71713-5"},{"key":"rf9","doi-asserted-by":"publisher","DOI":"10.5121\/ijcsit.2010.2509"},{"key":"rf10","doi-asserted-by":"publisher","DOI":"10.5573\/JSTS.2010.10.1.055"},{"key":"rf11","doi-asserted-by":"publisher","DOI":"10.1109\/4.661212"},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2345295"},{"key":"rf13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.821776"},{"key":"rf14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164009"},{"key":"rf15","doi-asserted-by":"publisher","DOI":"10.1109\/4.597298"},{"key":"rf16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.887807"},{"key":"rf17","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2010.0340"},{"key":"rf18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2007564"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126615501248","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T08:15:15Z","timestamp":1565079315000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126615501248"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,8,12]]},"references-count":17,"journal-issue":{"issue":"08","published-online":{"date-parts":[[2015,8,12]]},"published-print":{"date-parts":[[2015,9]]}},"alternative-id":["10.1142\/S0218126615501248"],"URL":"https:\/\/doi.org\/10.1142\/s0218126615501248","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,8,12]]}}}