{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,29]],"date-time":"2023-09-29T12:54:30Z","timestamp":1695992070651},"reference-count":7,"publisher":"World Scientific Pub Co Pte Lt","issue":"09","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2015,10]]},"abstract":"<jats:p> Over time, more and more systems are becoming mixed-criticality systems. As the complexity and size of these systems grow, computation\/communication resources should be more efficient than with traditional systems. Time-triggered (TT) Ethernet is a communication infrastructure that enables the use of a single physical communication infrastructure for distributed mixed-criticality applications while providing timely determinism. TTEthernet distinguishes between two traffic categories: The standard event-triggered (ET) traffic and the TT traffic. The latter, for which higher priority is granted, is subject to strong timing guarantees because of strict-periodicity constraint which fixes start-time cycles of TT messages. In addition, messages in an ET Ethernet traffic, which are of lower priority, have a minimum time interval between their transmission. The focus of this paper is on the timing analysis of a TTEthernet traffic by proposing: (i) A feasibility condition allowing to assess the timing requirements of TT messages. (ii) A schedulability condition allowing to check the schedulability of ET messages by taking into account of TT messages scheduling and idle times. <\/jats:p>","DOI":"10.1142\/s0218126615501406","type":"journal-article","created":{"date-parts":[[2015,7,13]],"date-time":"2015-07-13T10:40:06Z","timestamp":1436784006000},"page":"1550140","source":"Crossref","is-referenced-by-count":8,"title":["Timing Analysis of TTEthernet Traffic"],"prefix":"10.1142","volume":"24","author":[{"given":"Omar","family":"Kermia","sequence":"first","affiliation":[{"name":"Real-Time Embedded Systems Team, ASM Division, Centre de D\u00e9veloppement des Technologies Avanc\u00e9es (CDTA), Algiers, Algeria"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2015,8,27]]},"reference":[{"key":"rf1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01995673"},{"key":"rf9","doi-asserted-by":"publisher","DOI":"10.1145\/321738.321743"},{"key":"rf10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70787"},{"key":"rf15","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-012-9148-y"},{"key":"rf28","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.1028475"},{"key":"rf38","doi-asserted-by":"publisher","DOI":"10.1006\/inco.1995.1028"},{"key":"rf39","doi-asserted-by":"publisher","DOI":"10.1007\/BF01940882"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126615501406","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T17:43:06Z","timestamp":1565113386000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126615501406"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,8,27]]},"references-count":7,"journal-issue":{"issue":"09","published-online":{"date-parts":[[2015,8,27]]},"published-print":{"date-parts":[[2015,10]]}},"alternative-id":["10.1142\/S0218126615501406"],"URL":"https:\/\/doi.org\/10.1142\/s0218126615501406","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,8,27]]}}}