{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,30]],"date-time":"2025-10-30T22:31:15Z","timestamp":1761863475131},"reference-count":14,"publisher":"World Scientific Pub Co Pte Lt","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2015,12]]},"abstract":"<jats:p> Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to face. This paper presents an inexpensive instruction set extensions (ISE) of efficient cryptographic algorithms on 32-bit processors assuring various types of instruction (public\/private key cryptography, random number generator (RNG) and secure hash function (SHF)). These extensions provide hardware instructions that implement a full algorithm in a single instruction. Our enhanced LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40-nm technology. The total area of the resulting chip is about 1.93 mm<jats:sup>2<\/jats:sup> and the estimated power consumption of the chip is 16.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies and the achieved results show that our circuit is able to be arranged in many security constrained devices. <\/jats:p>","DOI":"10.1142\/s0218126615501583","type":"journal-article","created":{"date-parts":[[2015,9,18]],"date-time":"2015-09-18T10:42:27Z","timestamp":1442572947000},"page":"1550158","source":"Crossref","is-referenced-by-count":1,"title":["Enhancing a 32-Bit Processor Core with Efficient Cryptographic Instructions"],"prefix":"10.1142","volume":"24","author":[{"given":"Noura","family":"Benhadjyoussef","sequence":"first","affiliation":[{"name":"Electronics and Micro-Electronics Laboratory (E. \u03bc. E. L), Physics Department, Faculty of Sciences of Monastir, University of Monastir, Monastir 5019, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wajih","family":"Elhadjyoussef","sequence":"additional","affiliation":[{"name":"Electronics and Micro-Electronics Laboratory (E. \u03bc. E. L), Physics Department, Faculty of Sciences of Monastir, University of Monastir, Monastir 5019, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohsen","family":"Machhout","sequence":"additional","affiliation":[{"name":"Electronics and Micro-Electronics Laboratory (E. \u03bc. E. L), Physics Department, Faculty of Sciences of Monastir, University of Monastir, Monastir 5019, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rached","family":"Tourki","sequence":"additional","affiliation":[{"name":"Electronics and Micro-Electronics Laboratory (E. \u03bc. E. L), Physics Department, Faculty of Sciences of Monastir, University of Monastir, Monastir 5019, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kholdoun","family":"Torki","sequence":"additional","affiliation":[{"name":"Circuits Multi-Project (CMP), 46, Avenue F\u00e9lix Viallet, 38031 Grenoble Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2015,10,25]]},"reference":[{"key":"rf1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0165"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1145\/1080695.1069993"},{"key":"rf6","volume-title":"Customizable Embedded Processors: Design Technologies and Applications","author":"Paolo I.","year":"2007"},{"key":"rf15","doi-asserted-by":"publisher","DOI":"10.1007\/11604938_16"},{"key":"rf16","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-009-0398-4"},{"key":"rf17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70832"},{"key":"rf35","doi-asserted-by":"publisher","DOI":"10.1080\/19393551003649016"},{"key":"rf37","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-011-0005-z"},{"key":"rf43","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840415"},{"key":"rf44","volume-title":"Power Analysis Attacks: Revealing the Secrets of Smart Cards","author":"Mangard S.","year":"2007"},{"key":"rf47","doi-asserted-by":"publisher","DOI":"10.12720\/ijeee.1.1.39-43"},{"key":"rf48","unstructured":"D.\u00a0Sauveron, Computational Intelligence in Information Assurance and Security (Springer, 2007)\u00a0pp. 201\u2013237."},{"key":"rf49","doi-asserted-by":"crossref","unstructured":"S.\u00a0Abughazalah, K.\u00a0Markantonakis and K.\u00a0Mayes, Data Privacy Management, Autonomous Spontaneous Security, and Security Assurance (Springer International Publishing, 2015)\u00a0pp. 147\u2013164.","DOI":"10.1007\/978-3-319-17016-9_10"},{"key":"rf50","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-7915-4_14"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126615501583","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T13:20:53Z","timestamp":1565097653000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126615501583"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10,25]]},"references-count":14,"journal-issue":{"issue":"10","published-online":{"date-parts":[[2015,10,25]]},"published-print":{"date-parts":[[2015,12]]}},"alternative-id":["10.1142\/S0218126615501583"],"URL":"https:\/\/doi.org\/10.1142\/s0218126615501583","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,10,25]]}}}