{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,5,30]],"date-time":"2023-05-30T02:09:24Z","timestamp":1685412564848},"reference-count":13,"publisher":"World Scientific Pub Co Pte Lt","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2015,12]]},"abstract":"<jats:p> This paper shows that a conventional semi-custom design-flow based on a energy efficient adiabatic logic (EEAL) cell library allows any VLSI designer to design and verify complex adiabatic arithmetic units in a simple way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom EEAL-based 32-bit carry-lookahead adder (CLA) has been designed in a TSMC 90-nm CMOS process technology and verified by CADENCE Design suite. Differential cascode voltage swing (DCVS) logic has been used to implement the newly proposed EEAL and it uses only a sinusoidal clock supply to ensure correct operation. Post-layout simulations show that semi-custom adiabatic arithmetic units can save significant amount of energy, as compared to the previously reported single clocked adiabatic logic and logically equivalent static CMOS implementation. Extensive CADENCE simulations have been done for the verification of the functionality of the proposed logic structure. <\/jats:p>","DOI":"10.1142\/s0218126615501601","type":"journal-article","created":{"date-parts":[[2015,9,18]],"date-time":"2015-09-18T06:42:27Z","timestamp":1442558547000},"page":"1550160","source":"Crossref","is-referenced-by-count":3,"title":["Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application"],"prefix":"10.1142","volume":"24","author":[{"given":"Manash","family":"Chanda","sequence":"first","affiliation":[{"name":"Nano-device Simulation Lab, Department of ETCE, Jadavpur University, Kolkata 700032, West Bengal, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Swapnadip","family":"De","sequence":"additional","affiliation":[{"name":"Nano-device Simulation Lab, Department of ETCE, Jadavpur University, Kolkata 700032, West Bengal, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chandan Kumar","family":"Sarkar","sequence":"additional","affiliation":[{"name":"Nano-device Simulation Lab, Department of ETCE, Jadavpur University, Kolkata 700032, West Bengal, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2015,10,25]]},"reference":[{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1109\/92.863629"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.819573"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1109\/82.633443"},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126610006098"},{"key":"rf9","doi-asserted-by":"publisher","DOI":"10.1109\/4.766827"},{"key":"rf11","doi-asserted-by":"publisher","DOI":"10.1049\/el:19961272"},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1109\/4.499727"},{"key":"rf13","first-page":"1837","volume":"87","author":"Nakata S.","year":"2004","journal-title":"IEICE Trans. Electron. E"},{"key":"rf17","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"Rabaey J. M.","year":"2008"},{"key":"rf18","volume-title":"CMOS VLSI Design: A Circuits and System Perspective","author":"Neil J.","year":"2008"},{"key":"rf19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859471"},{"key":"rf21","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20010439"},{"key":"rf30","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20000381"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126615501601","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T09:20:55Z","timestamp":1565083255000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126615501601"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10,25]]},"references-count":13,"journal-issue":{"issue":"10","published-online":{"date-parts":[[2015,10,25]]},"published-print":{"date-parts":[[2015,12]]}},"alternative-id":["10.1142\/S0218126615501601"],"URL":"https:\/\/doi.org\/10.1142\/s0218126615501601","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,10,25]]}}}