{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T04:18:15Z","timestamp":1648959495649},"reference-count":17,"publisher":"World Scientific Pub Co Pte Lt","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2016,3]]},"abstract":"<jats:p> An asynchronous projection and summation circuit is proposed for single photon avalanche diode (SPAD) sensors. Thanks to the efficient interconnection by the asynchronous technique, the circuit can be easily implemented inside 2D SPAD arrays. As a result, the precise summation of the 1b data in one row can be parallel processed for all rows within the same cycle. A test-of-concept chip was fabricated in a 0.18[Formula: see text][Formula: see text]m 1P5M CMOS process. By measurement results, the summation of a 15-pixel row can be achieved by the proposed circuit within 20.5[Formula: see text]ns. Such a speed is very important for SPAD-based sensors that need fast summation operations. <\/jats:p>","DOI":"10.1142\/s021812661640017x","type":"journal-article","created":{"date-parts":[[2015,10,5]],"date-time":"2015-10-05T03:19:21Z","timestamp":1444015161000},"page":"1640017","source":"Crossref","is-referenced-by-count":1,"title":["An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors"],"prefix":"10.1142","volume":"25","author":[{"given":"Xiao","family":"Yang","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan"}]},{"given":"Hongbo","family":"Zhu","sequence":"additional","affiliation":[{"name":"VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, Japan"}]},{"given":"Toru","family":"Nakura","sequence":"additional","affiliation":[{"name":"VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, Japan"}]},{"given":"Tetsuya","family":"Iizuka","sequence":"additional","affiliation":[{"name":"VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, Japan"}]},{"given":"Kunihiro","family":"Asada","sequence":"additional","affiliation":[{"name":"VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, Japan"}]}],"member":"219","published-online":{"date-parts":[[2015,12,28]]},"reference":[{"key":"S021812661640017XBIB001","doi-asserted-by":"publisher","DOI":"10.1016\/j.sna.2007.06.021"},{"key":"S021812661640017XBIB002","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2007.902088"},{"key":"S021812661640017XBIB003","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2004.833975"},{"key":"S021812661640017XBIB004","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2014.2328440"},{"key":"S021812661640017XBIB005","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2014.2358685"},{"key":"S021812661640017XBIB006","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2014.2344034"},{"key":"S021812661640017XBIB007","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2284352"},{"key":"S021812661640017XBIB008","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2227607"},{"key":"S021812661640017XBIB009","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2014.2342197"},{"key":"S021812661640017XBIB011","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2284351"},{"key":"S021812661640017XBIB014","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2010.2064788"},{"key":"S021812661640017XBIB015","doi-asserted-by":"publisher","DOI":"10.1063\/1.1702936"},{"key":"S021812661640017XBIB016","first-page":"1","author":"Tetrault M.","year":"2015","journal-title":"IEEE Trans. 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