{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T08:58:02Z","timestamp":1649062682397},"reference-count":18,"publisher":"World Scientific Pub Co Pte Lt","issue":"04","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2016,4]]},"abstract":"<jats:p> Nowadays, it is desirable to generate traffic which can reflect realistic network traffic environment for performance evaluation of network equipments. Existing traffic generation solutions mainly include special test equipments, software traffic generators and field programmable gate array (FPGA)-based traffic generators. However, special test equipments are generally too expensive, software traffic generators could not achieve high data rates and FPGA-based traffic generators mostly lack flexibility. This paper presents a novel traffic generation solution according to an aggregated process-based model to overcome the weakness of above methods. The traffic generator can generate real-time Poisson, two-state Markov-modulated Poisson process (MMPP-2) and self-similar traffic by hardware. The main structure of the traffic generator is presented and statistical properties of the generated traffic have been evaluated. Experiment results indicate that the proposed traffic generation solution can achieve better performance of the generated traffic compared with existing FPGA-based traffic generators while the required date rates can be up to Gbps line rate. <\/jats:p>","DOI":"10.1142\/s0218126616500183","type":"journal-article","created":{"date-parts":[[2015,10,15]],"date-time":"2015-10-15T04:25:24Z","timestamp":1444883124000},"page":"1650018","source":"Crossref","is-referenced-by-count":1,"title":["An Aggregated Process-Based Traffic Generator for Network Performance Evaluation"],"prefix":"10.1142","volume":"25","author":[{"given":"Xiaoting","family":"Wang","sequence":"first","affiliation":[{"name":"State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, No. 4, Section 2, North Jianshe Road, Chengdu 610054, P. R. China"}]},{"given":"Yiwen","family":"Wang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, No. 4, Section 2, North Jianshe Road, Chengdu 610054, P. R. China"}]},{"given":"Ping","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, No. 4, Section 2, North Jianshe Road, Chengdu 610054, P. R. China"}]}],"member":"219","published-online":{"date-parts":[[2016,2,2]]},"reference":[{"key":"S0218126616500183BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1179894"},{"key":"S0218126616500183BIB005","doi-asserted-by":"publisher","DOI":"10.1002\/0470113952"},{"key":"S0218126616500183BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/MNET.2003.1233917"},{"key":"S0218126616500183BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/LCOMM.2004.832733"},{"key":"S0218126616500183BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.140"},{"key":"S0218126616500183BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2003.810315"},{"key":"S0218126616500183BIB014","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-006-0798-1"},{"key":"S0218126616500183BIB017","doi-asserted-by":"publisher","DOI":"10.1016\/j.peva.2011.07.003"},{"key":"S0218126616500183BIB018","doi-asserted-by":"publisher","DOI":"10.1109\/35.267444"},{"key":"S0218126616500183BIB020","volume-title":"Nonlinear Estimation and Classification","author":"Cao J.","year":"2002"},{"key":"S0218126616500183BIB021","doi-asserted-by":"publisher","DOI":"10.1109\/35.601746"},{"key":"S0218126616500183BIB022","doi-asserted-by":"publisher","DOI":"10.1109\/90.282603"},{"key":"S0218126616500183BIB023","doi-asserted-by":"publisher","DOI":"10.1109\/90.554723"},{"key":"S0218126616500183BIB025","doi-asserted-by":"publisher","DOI":"10.1109\/90.650143"},{"key":"S0218126616500183BIB028","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-014-9917-z"},{"key":"S0218126616500183BIB029","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"Rabaey J.","year":"2003","edition":"2"},{"key":"S0218126616500183BIB033","first-page":"39","volume":"1","author":"Pan C.","year":"2013","journal-title":"J. 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