{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:37:51Z","timestamp":1740116271477,"version":"3.37.3"},"reference-count":9,"publisher":"World Scientific Pub Co Pte Ltd","issue":"05","funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China (CN)","doi-asserted-by":"publisher","award":["61404090"],"award-info":[{"award-number":["61404090"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China (CN)","doi-asserted-by":"publisher","award":["61434004"],"award-info":[{"award-number":["61434004"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2016,5]]},"abstract":"<jats:p> This paper presents the design and implementation of an extended-counting incremental sigma\u2013delta ADC (IDC) with hardware-reuse technique. The proposed ADC architecture is a cascaded configuration of a second-order IDC and a two-stage cyclic ADC. The operation of the ADC consists of the \u201ccoarse phase\u201d and the \u201cfine phase\u201d. In the \u201ccoarse phase\u201d, the circuit works as an IDC to achieve the most significant bits (MSBs) and produce the residue voltage. Then in the \u201cfine phase\u201d, it is reused and changed to work as a cyclic ADC to quantize the residue voltage and achieve the least significant bits (LSBs). Eventual digital output is achieved by combining the two parts together. The utilization of extended-counting technique significantly reduces the conversion time and increases the conversion rate, and the hardware-reuse technique removes the demand for additional circuit area. The ADC is designed in 0.5[Formula: see text][Formula: see text]m CMOS process, which has a conversion rate of 43.48[Formula: see text]kS\/s with oversampling ratio (OSR) of 23 and achieves 84.83[Formula: see text]dB SNDR and 13.799-bit ENOB. It consumes 2.4[Formula: see text]mW with a 5[Formula: see text]V voltage supply, and the FOM is 3.87[Formula: see text]pJ\/step. <\/jats:p>","DOI":"10.1142\/s0218126616500389","type":"journal-article","created":{"date-parts":[[2016,1,4]],"date-time":"2016-01-04T04:08:53Z","timestamp":1451880533000},"page":"1650038","source":"Crossref","is-referenced-by-count":0,"title":["An Extended-Counting Incremental Sigma\u2013Delta ADC with Hardware-Reuse Technique"],"prefix":"10.1142","volume":"25","author":[{"given":"Xinji","family":"Zeng","sequence":"first","affiliation":[{"name":"School of Electronic Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin 300072, P.\u00a0R.\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8619-0620","authenticated-orcid":false,"given":"Jing","family":"Gao","sequence":"additional","affiliation":[{"name":"School of Electronic Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin 300072, P.\u00a0R.\u00a0China"}]},{"given":"Liu","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Electronic Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin 300072, P.\u00a0R.\u00a0China"}]},{"given":"Jiangtao","family":"Xu","sequence":"additional","affiliation":[{"name":"School of Electronic Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin 300072, P.\u00a0R.\u00a0China"}]}],"member":"219","published-online":{"date-parts":[[2016,2,25]]},"reference":[{"key":"S0218126616500389BIB001","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.826202"},{"key":"S0218126616500389BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891701"},{"key":"S0218126616500389BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884332"},{"key":"S0218126616500389BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/82.663805"},{"key":"S0218126616500389BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/4.902758"},{"key":"S0218126616500389BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.873891"},{"key":"S0218126616500389BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2097716"},{"key":"S0218126616500389BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048493"},{"key":"S0218126616500389BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822903"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126616500389","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,23]],"date-time":"2019-09-23T16:44:10Z","timestamp":1569257050000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126616500389"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,2,25]]},"references-count":9,"journal-issue":{"issue":"05","published-online":{"date-parts":[[2016,2,25]]},"published-print":{"date-parts":[[2016,5]]}},"alternative-id":["10.1142\/S0218126616500389"],"URL":"https:\/\/doi.org\/10.1142\/s0218126616500389","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2016,2,25]]}}}