{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:37:51Z","timestamp":1740116271877,"version":"3.37.3"},"reference-count":4,"publisher":"World Scientific Pub Co Pte Ltd","issue":"07","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2016,7]]},"abstract":"<jats:p> The integrity verification of on-chip flash memory data as code memory is becoming important in microcontroller-based applications such as automotive systems. On-the-fly memory fail-detection requires a fast detection method in the seamless background mode without any interruption of CPU operation and low-power flash access hardware to provide safety-conscious execution of the user-programmed firmware during system operations. In this paper, newly-designed read-path architecture based on the binary inversion techniques is proposed for on-chip flash-embedded microcontrollers. The proposed binary inversion method also enables fail-safe, low-power memory access with zero hardware overhead by embedding the scramble flags on the cyclic redundancy check (CRC) protection code. Time-multiplexed CRC calculation for bit-inversion binary code is automatically executed with the silent background mode during CPU idle time without any CPU wait cost. The implementation result shows that the de-inversion procedure could be achieved with just an additional 1,024 bits CRC data in the case of 64 sectors for 4 KB flash memory by reducing 75% of the area of the previous work. The code memory integrity verification time in the seamless background mode is about 30% of the conventional foreground method. The total average current during the code execution for Dhrystone<jats:sup>TM<\/jats:sup> benchmark uses just 15% of the basement. <\/jats:p>","DOI":"10.1142\/s0218126616500687","type":"journal-article","created":{"date-parts":[[2016,3,8]],"date-time":"2016-03-08T20:08:03Z","timestamp":1457467683000},"page":"1650068","source":"Crossref","is-referenced-by-count":0,"title":["Low-Power Code Memory Integrity Verification Using Background Cyclic Redundancy Check Calculator Based on Binary Code Inversion Method"],"prefix":"10.1142","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5560-873X","authenticated-orcid":false,"given":"Daejin","family":"Park","sequence":"first","affiliation":[{"name":"School of Electronics Engineering, College of IT Engineering, Kyungpook National University, 80 Daehakro, Bukgu, Daegu 41566, South Korea"}]}],"member":"219","published-online":{"date-parts":[[2016,4,22]]},"reference":[{"key":"S0218126616500687BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2008.83"},{"key":"S0218126616500687BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2265894"},{"key":"S0218126616500687BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.811704"},{"key":"S0218126616500687BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/4.871317"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126616500687","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T11:57:57Z","timestamp":1565179077000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126616500687"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4,22]]},"references-count":4,"journal-issue":{"issue":"07","published-online":{"date-parts":[[2016,4,22]]},"published-print":{"date-parts":[[2016,7]]}},"alternative-id":["10.1142\/S0218126616500687"],"URL":"https:\/\/doi.org\/10.1142\/s0218126616500687","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2016,4,22]]}}}