{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,12]],"date-time":"2026-10-12T20:53:16Z","timestamp":1791838396909,"version":"4.3.4"},"reference-count":20,"publisher":"World Scientific Pub Co Pte Ltd","issue":"11","funder":[{"DOI":"10.13039\/100006228","name":"Oak Ridge National Laboratory","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006228","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2016,11]]},"abstract":"<jats:p> Researchers have explored both volatile memories (e.g., SRAM and embedded DRAM) and nonvolatile memories (NVMs, such as resistive RAM) for design of on-chip caches. However, both volatile and nonvolatile memories present unique reliability challenges. NVMs are immune to radiation-induced soft errors, however, due to their limited write endurance, they are vulnerable to hard errors under nonuniform write distribution. By contrast, SRAM has high write endurance but is susceptible to soft errors due to cosmic radiation. SRAM\u2013NVM hybrid caches and the management techniques for them aim to bring the best of SRAM and NVM together, however, the reliability implications of them have not been well understood. In this paper, we show that there are inherent tradeoffs in improving resilience to hard and soft errors in hybrid caches such that mitigating one may result in aggravating another. We confirm this by experiments with two recent hybrid cache management techniques. We also re-examine cache design trends in modern processors from reliability perspective. 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