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Later on, prototype design through field-programmable gate array (FPGA) is developed for a (256 \u00d7 256), 8-bit gray scale image using (32 \u00d7 32) image block and pipeline architecture. For a cover image of size (256 \u00d7 256), the proposed architecture requires 8,971 slices, 8,246 slice flip-flops, 9,706 numbers of four-input LUTs and 2 FIFO 16\/RAMB for watermark embedding purpose. Proposed architecture consumes a power of 636[Formula: see text]mW and offers a data rate of 1.0493[Formula: see text]Mbps at an operating frequency as high as 95.3[Formula: see text]MHz. <\/jats:p>","DOI":"10.1142\/s021812661750044x","type":"journal-article","created":{"date-parts":[[2016,10,7]],"date-time":"2016-10-07T02:15:14Z","timestamp":1475806514000},"page":"1750044","source":"Crossref","is-referenced-by-count":5,"title":["FPGA Implementation for Modified RCM-RW on Digital Images"],"prefix":"10.1142","volume":"26","author":[{"given":"Hirak Kumar","family":"Maity","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, College of Engineering and Management, Kolaghat, K.T.P.P.\u00a0Township, Purba Medinipur 721171, West Bengal, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Santi P.","family":"Maity","sequence":"additional","affiliation":[{"name":"Department of Information Technology, Indian Institute of Engineering Science and Technology, Shibpur, Botanic Garden, Howrah 711103, West Bengal, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2016,11,21]]},"reference":[{"key":"S021812661750044XBIB001","first-page":"134546","volume":"2010","author":"Caldelli R.","year":"2010","journal-title":"EURASIP J. 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