{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T05:56:19Z","timestamp":1648533379238},"reference-count":7,"publisher":"World Scientific Pub Co Pte Lt","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2017,11]]},"abstract":"<jats:p> This paper presents a fully differential class-AB current mirror OTA that improves the common-mode behavior of a topology that presents very good differential-mode performance but poor common-mode rejection ratio (CMRR). The proposed solution requires a low-current auxiliary circuit driven by the input signal, to compensate the effect of the common-mode input component. Simulations in 40-nm CMOS technology show a net reduction of common-mode gain of more than 90[Formula: see text]dB without affecting the differential-mode behavior; a sample-and-hold amplifier exploiting the proposed amplifier has also been simulated. <\/jats:p>","DOI":"10.1142\/s0218126617501699","type":"journal-article","created":{"date-parts":[[2017,4,11]],"date-time":"2017-04-11T03:35:54Z","timestamp":1491881754000},"page":"1750169","source":"Crossref","is-referenced-by-count":1,"title":["Fully Differential Class-AB OTA with Improved CMRR"],"prefix":"10.1142","volume":"26","author":[{"given":"Francesco","family":"Centurelli","sequence":"first","affiliation":[{"name":"Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy"}]},{"given":"Pietro","family":"Monsurr\u00f2","sequence":"additional","affiliation":[{"name":"Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy"}]},{"given":"Gaetano","family":"Parisi","sequence":"additional","affiliation":[{"name":"Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy"}]},{"given":"Pasquale","family":"Tommasino","sequence":"additional","affiliation":[{"name":"Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy"}]},{"given":"Alessandro","family":"Trifiletti","sequence":"additional","affiliation":[{"name":"Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy"}]}],"member":"219","published-online":{"date-parts":[[2017,4,11]]},"reference":[{"key":"S0218126617501699BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2020945"},{"key":"S0218126617501699BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2194191"},{"key":"S0218126617501699BIB004","volume-title":"Analog Integrated Circuit Design","author":"Johns D. A.","year":"1997"},{"key":"S0218126617501699BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1985.1052449"},{"key":"S0218126617501699BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/4.32035"},{"key":"S0218126617501699BIB008","doi-asserted-by":"publisher","DOI":"10.1049\/el:19970964"},{"key":"S0218126617501699BIB009","doi-asserted-by":"publisher","DOI":"10.1002\/cta.2123"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126617501699","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T12:07:39Z","timestamp":1565093259000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126617501699"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4,11]]},"references-count":7,"journal-issue":{"issue":"11","published-online":{"date-parts":[[2017,3,28]]},"published-print":{"date-parts":[[2017,11]]}},"alternative-id":["10.1142\/S0218126617501699"],"URL":"https:\/\/doi.org\/10.1142\/s0218126617501699","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,4,11]]}}}