{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T16:03:31Z","timestamp":1783613011262,"version":"3.55.0"},"reference-count":14,"publisher":"World Scientific Pub Co Pte Lt","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2017,11]]},"abstract":"<jats:p> A precharged CMOS high-performance phase frequency detector (PFD) circuit is presented in this paper. The PFD consists of two identical building blocks. Each PFD block generates UP or DOWN signal and consists of [Formula: see text]- and [Formula: see text]-precharge stages connected in cascade. The proposed PFD circuit has no feedback path and has zero dead-zone in the phase characteristic, what is important in low jitter applications. It also has minimal blind-zone (extended input detection range) close to the limit imposed by the used CMOS technology. The PFD is designed in 0.13[Formula: see text][Formula: see text]m BiCMOS technology and has 1.8[Formula: see text]V supply voltage. The simulation results of blind-zone values are within the range from [Formula: see text] for 1[Formula: see text]GHz up to [Formula: see text] for 8[Formula: see text]GHz. This circuit can be used in applications for high-frequency and low-power delay locked loop and phase locked loop circuits, effectively. <\/jats:p>","DOI":"10.1142\/s0218126617501791","type":"journal-article","created":{"date-parts":[[2017,4,7]],"date-time":"2017-04-07T03:38:50Z","timestamp":1491536330000},"page":"1750179","source":"Crossref","is-referenced-by-count":18,"title":["Precharged Phase Detector with Zero Dead-Zone and Minimal Blind-Zone"],"prefix":"10.1142","volume":"26","author":[{"given":"Goran","family":"Nikoli\u0107","sequence":"first","affiliation":[{"name":"Faculty of Electronic Engineering, University of Ni\u0161, Aleksandra Medvedeva 14, 18000 Ni\u0161, Serbia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Goran","family":"Jovanovi\u0107","sequence":"additional","affiliation":[{"name":"Faculty of Electronic Engineering, University of Ni\u0161, Aleksandra Medvedeva 14, 18000 Ni\u0161, Serbia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mile","family":"Stoj\u010dev","sequence":"additional","affiliation":[{"name":"Faculty of Electronic Engineering, University of Ni\u0161, Aleksandra Medvedeva 14, 18000 Ni\u0161, Serbia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tatjana","family":"Nikoli\u0107","sequence":"additional","affiliation":[{"name":"Faculty of Electronic Engineering, University of Ni\u0161, Aleksandra Medvedeva 14, 18000 Ni\u0161, Serbia"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"219","published-online":{"date-parts":[[2017,4,6]]},"reference":[{"key":"S0218126617501791BIB001","volume-title":"Phase-Locking in High-Performance Systems: From Devices to Architectures","author":"Razavi B.","year":"2001"},{"key":"S0218126617501791BIB002","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2007.02.025"},{"key":"S0218126617501791BIB003","doi-asserted-by":"publisher","DOI":"10.5121\/acij.2011.2605"},{"key":"S0218126617501791BIB006","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-8628-0"},{"key":"S0218126617501791BIB011","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803048"},{"key":"S0218126617501791BIB012","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2087951"},{"key":"S0218126617501791BIB013","doi-asserted-by":"publisher","DOI":"10.1109\/4.826820"},{"key":"S0218126617501791BIB014","doi-asserted-by":"publisher","DOI":"10.1109\/4.658634"},{"key":"S0218126617501791BIB017","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126615501042"},{"key":"S0218126617501791BIB018","volume-title":"Principles of CMOS VLSI Design","author":"Weste N. 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