{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:37:39Z","timestamp":1740116259286,"version":"3.37.3"},"reference-count":6,"publisher":"World Scientific Pub Co Pte Ltd","issue":"03","funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61376025"],"award-info":[{"award-number":["61376025"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004608","name":"Natural Science Foundation of Jiangsu Province","doi-asserted-by":"publisher","award":["BK20160806"],"award-info":[{"award-number":["BK20160806"]}],"id":[{"id":"10.13039\/501100004608","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,3]]},"abstract":"<jats:p> This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO\/FI function by re-utilizing S9\/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND\/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds implementation. On the other hand, the proposed architecture 2 uses a single FO\/FI function for both MISTY1 round function as well as extended key generation and can be employed for MISTY1 [Formula: see text] rounds. To analyze the performance and covered area for ASICs, Synopsys Design Complier, SMIC 0.18[Formula: see text][Formula: see text]m @ 1.8[Formula: see text]V is used. The hardware constituted 3041 and 2331 NAND gates achieving throughput of 171 and 166 Mbps for 8 rounds implementation of architectures 1 and 2, respectively. Comprehensive analysis of proposed designs is covered in this paper. <\/jats:p>","DOI":"10.1142\/s0218126618500378","type":"journal-article","created":{"date-parts":[[2017,6,30]],"date-time":"2017-06-30T04:38:54Z","timestamp":1498797534000},"page":"1850037","source":"Crossref","is-referenced-by-count":5,"title":["Compact Hardware Implementations of MISTY1 Block Cipher"],"prefix":"10.1142","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2717-0272","authenticated-orcid":false,"family":"Yasir","sequence":"first","affiliation":[{"name":"College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, No. 29 Yudao Street, Nanjing 210016, Jiangsu Province, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ning","family":"Wu","sequence":"additional","affiliation":[{"name":"College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, No. 29 Yudao Street, Nanjing 210016, Jiangsu Province, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoqiang","family":"Zhang","sequence":"additional","affiliation":[{"name":"College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, No. 29 Yudao Street, Nanjing 210016, Jiangsu Province, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2017,10,30]]},"reference":[{"key":"S0218126618500378BIB005","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E93.A.3"},{"key":"S0218126618500378BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2419623"},{"key":"S0218126618500378BIB010","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E94.A.2628"},{"key":"S0218126618500378BIB013","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126616500377"},{"key":"S0218126618500378BIB014","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126606003362"},{"key":"S0218126618500378BIB016","doi-asserted-by":"publisher","DOI":"10.1587\/elex.11.20140934"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126618500378","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,23]],"date-time":"2019-09-23T09:43:25Z","timestamp":1569231805000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126618500378"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10,30]]},"references-count":6,"journal-issue":{"issue":"03","published-online":{"date-parts":[[2017,10,30]]},"published-print":{"date-parts":[[2018,3]]}},"alternative-id":["10.1142\/S0218126618500378"],"URL":"https:\/\/doi.org\/10.1142\/s0218126618500378","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2017,10,30]]}}}