{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T08:13:13Z","timestamp":1761293593968,"version":"3.37.3"},"reference-count":19,"publisher":"World Scientific Pub Co Pte Ltd","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,3]]},"abstract":"<jats:p> A new method for reducing power consumption in finite state machines (FSMs) is proposed. Probabilistic description of the FSMs is the theoretical background of power-oriented state assignment. The algorithm of state assignment is based on a decomposition strategy of coding. This idea uses a binary tree in which nodes are created by sharing a finite state machine. The algorithm has been applied to the LGSynth91 benchmark and has also been compared to other approaches. The experiments showed that the proposed method leads to a reduction in power consumption compared to the state encoding algorithms that have already been developed. Reduction of the circuits\u2019 area is also observed. <\/jats:p>","DOI":"10.1142\/s021812661850041x","type":"journal-article","created":{"date-parts":[[2017,7,6]],"date-time":"2017-07-06T23:08:08Z","timestamp":1499382488000},"page":"1850041","source":"Crossref","is-referenced-by-count":14,"title":["Low Power Synthesis of Finite State Machines\u00a0\u2014 State Assignment Decomposition Algorithm"],"prefix":"10.1142","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8739-1224","authenticated-orcid":false,"given":"Krzysztof","family":"Kajstura","sequence":"first","affiliation":[{"name":"Department of Computer Science and Automatics, University of Bielsko-Biala, Willowa 2, Bielsko-Bia\u0142a, 43-309, Poland"}]},{"given":"Dariusz","family":"Kania","sequence":"additional","affiliation":[{"name":"Institute of Electronics, Silesian University of Technology, Akademicka 16, Gliwice, 44-100, Poland"}]}],"member":"219","published-online":{"date-parts":[[2017,10,30]]},"reference":[{"key":"S021812661850041XBIB002","doi-asserted-by":"publisher","DOI":"10.1109\/43.59068"},{"key":"S021812661850041XBIB003","doi-asserted-by":"publisher","DOI":"10.1109\/43.62787"},{"key":"S021812661850041XBIB004","doi-asserted-by":"publisher","DOI":"10.1109\/43.62788"},{"key":"S021812661850041XBIB006","doi-asserted-by":"publisher","DOI":"10.2478\/v10006-007-0046-8"},{"key":"S021812661850041XBIB007","doi-asserted-by":"publisher","DOI":"10.1109\/92.335011"},{"key":"S021812661850041XBIB008","doi-asserted-by":"publisher","DOI":"10.1109\/54.329451"},{"key":"S021812661850041XBIB009","doi-asserted-by":"publisher","DOI":"10.1109\/43.700725"},{"key":"S021812661850041XBIB011","doi-asserted-by":"publisher","DOI":"10.1109\/43.503933"},{"key":"S021812661850041XBIB012","doi-asserted-by":"publisher","DOI":"10.1109\/43.945307"},{"key":"S021812661850041XBIB013","doi-asserted-by":"publisher","DOI":"10.1049\/el:20052307"},{"key":"S021812661850041XBIB015","doi-asserted-by":"publisher","DOI":"10.1109\/4.364440"},{"key":"S021812661850041XBIB019","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20020431"},{"key":"S021812661850041XBIB021","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20010666"},{"key":"S021812661850041XBIB024","first-page":"521","volume":"97","author":"Surti P.","year":"1997","journal-title":"IEEE EDTC"},{"key":"S021812661850041XBIB026","doi-asserted-by":"publisher","DOI":"10.1109\/92.250198"},{"key":"S021812661850041XBIB028","first-page":"499","volume":"54","author":"Salauyou V.","year":"2008","journal-title":"Pomiary, Autom. Kontrola"},{"key":"S021812661850041XBIB030","first-page":"146","volume":"91","author":"Kajstura K.","year":"2015","journal-title":"Przegl\u0105d Elektrotechniczny"},{"key":"S021812661850041XBIB031","doi-asserted-by":"publisher","DOI":"10.1109\/4.293111"},{"volume-title":"Probability and Statistics with Reliability, Queuing and Computer Science Applications","year":"1982","author":"Trivedi K. S.","key":"S021812661850041XBIB035"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S021812661850041X","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T11:16:34Z","timestamp":1565090194000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S021812661850041X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10,30]]},"references-count":19,"journal-issue":{"issue":"03","published-online":{"date-parts":[[2017,10,30]]},"published-print":{"date-parts":[[2018,3]]}},"alternative-id":["10.1142\/S021812661850041X"],"URL":"https:\/\/doi.org\/10.1142\/s021812661850041x","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2017,10,30]]}}}