{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:37:57Z","timestamp":1740116277270,"version":"3.37.3"},"reference-count":11,"publisher":"World Scientific Pub Co Pte Ltd","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,5]]},"abstract":"<jats:p> In this brief, we present the design and evaluation of a high speed and energy-efficient truncated multiplier for unsigned multiplication, such that the average absolute error due to truncation and rounding is kept minimal. The proposed algorithm eliminates a few least significant Partial Product (PP) bits and adds correction bias at appropriate PP bit positions to minimize the total error. From the literatures reviewed, it is clear that there is scope for reducing delay in multiplication using sutras of ancient vedic mathematics. This work uses a simple \u201ccrosswise and vertical sutra\u201d of Vedic mathematics to generate PP bits. The proposed methodology groups the input into [Formula: see text]\/2 bits, eliminates least subgroup multiplication ([Formula: see text]) and deletes few least significant bits in other subgroup multiplications to reduce area and power dissipation. In addition, correction biase are added at appropriate bit positions to reduce the overall absolute error due to the elimination of few PP bits and rounding of final product. Experimental evaluation of the proposed truncated design is carried out through structural level VHDL modeling and simulations using Synopsys design compiler. Performance analysis revealed Chip-Area Ratio (CAR%) to be 33.81% and Power-Delay Product (PDP) of 14.84[Formula: see text]pJ of proposed truncated design for an [Formula: see text] multiplication. <\/jats:p>","DOI":"10.1142\/s0218126618500779","type":"journal-article","created":{"date-parts":[[2017,9,25]],"date-time":"2017-09-25T02:07:38Z","timestamp":1506305258000},"page":"1850077","source":"Crossref","is-referenced-by-count":8,"title":["VLSI Implementation of High Speed Energy-Efficient Truncated Multiplier"],"prefix":"10.1142","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4540-9198","authenticated-orcid":false,"given":"K. N.","family":"Vijeyakumar","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, Coimbatore 642003, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Elango","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Coimbatore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Kalaiselvi","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, Coimbatore 642003, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2018,2,6]]},"reference":[{"key":"S0218126618500779BIB001","doi-asserted-by":"publisher","DOI":"10.1109\/12.166611"},{"key":"S0218126618500779BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/82.486455"},{"key":"S0218126618500779BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/82.769795"},{"key":"S0218126618500779BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2090572"},{"key":"S0218126618500779BIB008","doi-asserted-by":"publisher","DOI":"10.1049\/el:20061812"},{"key":"S0218126618500779BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/82.877155"},{"key":"S0218126618500779BIB012","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2148970"},{"volume-title":"Vedic Mathematics","year":"2009","author":"Maharaja J. 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Syst."}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126618500779","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T15:49:32Z","timestamp":1565106572000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126618500779"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2,6]]},"references-count":11,"journal-issue":{"issue":"05","published-online":{"date-parts":[[2018,2,6]]},"published-print":{"date-parts":[[2018,5]]}},"alternative-id":["10.1142\/S0218126618500779"],"URL":"https:\/\/doi.org\/10.1142\/s0218126618500779","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2018,2,6]]}}}