{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T05:16:13Z","timestamp":1774934173891,"version":"3.50.1"},"reference-count":25,"publisher":"World Scientific Pub Co Pte Lt","issue":"06","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,6,15]]},"abstract":"<jats:p> In recent days, there has been a growing interest in network-on-chip (NoC), as it offers a promising architecture for future systems on-chip (SoC). The performance degradation is the major problem in designing NoC, due to the complexity in designing a traffic generator and traffic estimator (TE) modules. In the conventional NoC design, new traffic modules and low-power algorithms (LPAS) are introduced. A LPA with an NoC has given performance degradation in the transmission rate, end-to-end delay and overall energy consumption. To address this power issue, we modeled the Menger\u2019s theorem (MT) (graph theory (GT))-based clock boosting mechanism to produce an effective frequency for the router. The following two methods are introduced to improve the performance of NoCs: (i) development of a real-time traffic generation module and software-based traffic estimator (STE) (ii) GT approach is introduced into a dynamic frequency scaling (DFS) LPA. In general, the frequency selection process during various traffic conditions in history-based dynamic voltage scaling algorithm (HDVS) and history-based DFS algorithm (HDFS) is more complex and it gives performance degradation. In the proposed method, MT-based DFS (MT-DFS) parameters are estimated under various conditions using both 65 and 90[Formula: see text]nm TSMC CMOS technology. In comparison with conventional HDFS, the evaluations show that MT-DFS interface achieves 67.7% energy saving, 85% dynamic power savings of the links in the on-chip network and 74.27% leakage power saving of the link. <\/jats:p>","DOI":"10.1142\/s0218126618500846","type":"journal-article","created":{"date-parts":[[2017,10,11]],"date-time":"2017-10-11T07:52:12Z","timestamp":1507708332000},"page":"1850084","source":"Crossref","is-referenced-by-count":2,"title":["BUTHA: Boost Up Clock Terminal with Heuristic Approach for NoC"],"prefix":"10.1142","volume":"27","author":[{"given":"Erulappan","family":"Sakthivel","sequence":"first","affiliation":[{"name":"Department of Electrical and Electronics, PSR Engineering College, Sivakasi, Tamil Nadu, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Veluchamy","family":"Malathi","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronics, Anna University, Regional Office, Madurai, Tamil Nadu, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Muruganantham","family":"Arunraja","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronics, PSR Engineering College, Sivakasi, Tamil Nadu, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2018,2,22]]},"reference":[{"key":"S0218126618500846BIB001","doi-asserted-by":"publisher","DOI":"10.1142\/S021812661540006X"},{"key":"S0218126618500846BIB002","doi-asserted-by":"publisher","DOI":"10.1145\/1108956.1108957"},{"key":"S0218126618500846BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/92.845896"},{"key":"S0218126618500846BIB006","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2012.12.014"},{"key":"S0218126618500846BIB008","doi-asserted-by":"publisher","DOI":"10.1142\/S021812661650050X"},{"key":"S0218126618500846BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.134"},{"key":"S0218126618500846BIB011","first-page":"173","author":"Azimi M.","year":"2007","journal-title":"Proc. Intel Technology J."},{"key":"S0218126618500846BIB013","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2009.01.002"},{"key":"S0218126618500846BIB014","doi-asserted-by":"publisher","DOI":"10.1093\/ietfec\/e88-a.12.3580"},{"key":"S0218126618500846BIB016","doi-asserted-by":"publisher","DOI":"10.1002\/047120644X"},{"key":"S0218126618500846BIB017","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2014.06.001"},{"key":"S0218126618500846BIB019","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839485"},{"key":"S0218126618500846BIB020","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126608004630"},{"key":"S0218126618500846BIB022","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2008.11.019"},{"key":"S0218126618500846BIB023","doi-asserted-by":"publisher","DOI":"10.1109\/12.67315"},{"key":"S0218126618500846BIB024","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2008.11.023"},{"key":"S0218126618500846BIB025","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2013.08.006"},{"key":"S0218126618500846BIB026","doi-asserted-by":"publisher","DOI":"10.1145\/1132952.1132953"},{"key":"S0218126618500846BIB027","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2178620"},{"key":"S0218126618500846BIB029","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2016.01.009"},{"key":"S0218126618500846BIB030","doi-asserted-by":"publisher","DOI":"10.1109\/71.127260"},{"key":"S0218126618500846BIB032","doi-asserted-by":"publisher","DOI":"10.1109\/65.580917"},{"key":"S0218126618500846BIB033","doi-asserted-by":"publisher","DOI":"10.1016\/0095-8956(87)90006-2"},{"key":"S0218126618500846BIB034","doi-asserted-by":"publisher","DOI":"10.1016\/S0012-365X(96)00129-X"},{"key":"S0218126618500846BIB035","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2034353"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126618500846","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T14:12:01Z","timestamp":1565187121000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126618500846"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2,22]]},"references-count":25,"journal-issue":{"issue":"06","published-online":{"date-parts":[[2018,2,22]]},"published-print":{"date-parts":[[2018,6,15]]}},"alternative-id":["10.1142\/S0218126618500846"],"URL":"https:\/\/doi.org\/10.1142\/s0218126618500846","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,2,22]]}}}