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The novel architecture achieves 81.25% reduction in capacitor area over the convention SAR. With the third reference voltage VCM and split-MSB switching procedure, the proposed switching scheme achieves 99.01% less switching energy over the convention SAR. Besides the significant energy saving, this asymmetric capacitor architecture also obtains a good performance in nonlinearity simulation. Based on the Matlab simulation for capacitor mismatch, the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.166LSB and 0.122LSB, respectively. <\/jats:p>","DOI":"10.1142\/s0218126618501098","type":"journal-article","created":{"date-parts":[[2017,11,9]],"date-time":"2017-11-09T21:44:20Z","timestamp":1510263860000},"page":"1850109","source":"Crossref","is-referenced-by-count":8,"title":["Energy-Efficient and Area-Saving Asymmetric Capacitor Switching Scheme for SAR ADCs"],"prefix":"10.1142","volume":"27","author":[{"given":"Hongzhi","family":"Liang","sequence":"first","affiliation":[{"name":"School of Microelectronics, Xidian University, No. 2 South Taibai Road, Xi\u2019an 710071, P. R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ruixue","family":"Ding","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Xidian University, No. 2 South Taibai Road, Xi\u2019an 710071, P. R. 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