{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,8]],"date-time":"2025-11-08T17:45:47Z","timestamp":1762623947547},"reference-count":16,"publisher":"World Scientific Pub Co Pte Lt","issue":"08","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,7]]},"abstract":"<jats:p> A PLL-based clock generator with an auto-calibration circuit is presented. The auto-calibration circuit employs an oscillator-based time-to-digital converter (TDC) to achieve a constant loop bandwidth and fast lock time. The TDC measures the operating frequency of [Formula: see text]-stage ring-VCO with a resolution of [Formula: see text] in a time period of [Formula: see text]. The measured frequency is utilized to calibrate loop bandwidth and VCO frequency. The clock generator is designed in 40[Formula: see text]nm CMOS process and operates from 1.2[Formula: see text]GHz to 3.6[Formula: see text]GHz with 8-phase outputs. The total lock time is less than 3[Formula: see text][Formula: see text]s including calibration and PLL closed-loop locking processes. Operating at 3.2[Formula: see text]GHz, the in-band phase noise is better than [Formula: see text][Formula: see text]dBc\/Hz and root-mean square (RMS) jitter integrated from 10[Formula: see text]KHz to 100[Formula: see text]MHz is 2 ps. In the entire operating range, the RMS jitter and reference spur are better than 5.5[Formula: see text]ps and [Formula: see text][Formula: see text]dBc\/Hz, respectively. The clock generator consumes only 3[Formula: see text]mW from 1.1[Formula: see text]V supply at high-frequency end and 1.6[Formula: see text]mW at low-frequency end. The active area is only 0.04[Formula: see text]mm<jats:sup>2<\/jats:sup> including on-chip loop filter and auto-calibration circuits. <\/jats:p>","DOI":"10.1142\/s0218126618501177","type":"journal-article","created":{"date-parts":[[2017,11,17]],"date-time":"2017-11-17T06:26:23Z","timestamp":1510899983000},"page":"1850117","source":"Crossref","is-referenced-by-count":4,"title":["A 3 mW 1.2\u20133.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth"],"prefix":"10.1142","volume":"27","author":[{"given":"Jili","family":"Zhang","sequence":"first","affiliation":[{"name":"Department of Electronic Science and Technology, University of Science and Technology of China, 433 Huangshan Rd, Hefei, Anhui 230027, P. R. China"}]},{"given":"Yu","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Electronic Science and Technology, University of Science and Technology of China, 433 Huangshan Rd, Hefei, Anhui 230027, P. R. China"}]},{"given":"Shengxi","family":"Diao","sequence":"additional","affiliation":[{"name":"Department of Electronic Science and Technology, University of Science and Technology of China, 433 Huangshan Rd, Hefei, Anhui 230027, P. R. China"}]},{"given":"Xuefei","family":"Bai","sequence":"additional","affiliation":[{"name":"Department of Electronic Science and Technology, University of Science and Technology of China, 433 Huangshan Rd, Hefei, Anhui 230027, P. R. China"}]},{"given":"Fujiang","family":"Lin","sequence":"additional","affiliation":[{"name":"Department of Electronic Science and Technology, University of Science and Technology of China, 433 Huangshan Rd, Hefei, Anhui 230027, P. R. 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