{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:16:23Z","timestamp":1758892583291},"reference-count":8,"publisher":"World Scientific Pub Co Pte Lt","issue":"08","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,7]]},"abstract":"<jats:p> The growing demand for high-performance digital circuits, mainly involving FPGAs, increases the demand for high-level synthesis (HLS) tools. Traditional Hardware Description Languages (HDLs) are complex and depend on low-level abstractions, thereby requiring hardware detailed knowledge from developers. In turn, the current HLS tools are based on proprietary or C\/C[Formula: see text] derived languages, which allow easier circuit description but decrease performance. This work presents an alternative solution for designing digital circuits, which arises from the Notification-Oriented Paradigm (NOP). The NOP is an alternative computing solution based upon a set of predefined interconnected entities whose collaborations are performed through precise notifications. The NOP, when targeted to digital hardware (DH), allows the developer to describe the circuit behavior just by connecting and parameterizing elements. The result is a VHDL file that can be compiled for any platform from any manufacturer. In order to check the functionality of this approach, sorting circuits were built both with usual VHDL and with the NOP VHDL aiming to compare the resulting circuits in terms of operating frequency and resource use. The results show that the NOP VHDL approach facilitates the build of digital circuits when compared to the VHDL usual approach without limiting the operating frequency or increasing the use of resources. <\/jats:p>","DOI":"10.1142\/s0218126618501244","type":"journal-article","created":{"date-parts":[[2017,11,16]],"date-time":"2017-11-16T01:52:45Z","timestamp":1510797165000},"page":"1850124","source":"Crossref","is-referenced-by-count":6,"title":["Notification-Oriented Paradigm to Implement Digital Hardware"],"prefix":"10.1142","volume":"27","author":[{"given":"Ricardo","family":"Kerschbaumer","sequence":"first","affiliation":[{"name":"Control and Automation Department, Federal Institute Catarinense (IFC), Rua Vig\u00e1rio Frei Jo\u00e3o, 550 Luzerna, SC 89609000, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robson R.","family":"Linhares","sequence":"additional","affiliation":[{"name":"Graduate School in Electrical Engineering and Industrial Computer Science (CPGEI), Graduate School of Applied Computing (PPGCA, DAINF, DAELN), Federal University of Technology \u2014 Paran\u00e1 (UTFPR), Av. 7 de setembro, 3165, Curitiba, PR 80230901, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean M.","family":"Sim\u00e3o","sequence":"additional","affiliation":[{"name":"Graduate School in Electrical Engineering and Industrial Computer Science (CPGEI), Graduate School of Applied Computing (PPGCA, DAINF, DAELN), Federal University of Technology \u2014 Paran\u00e1 (UTFPR), Av. 7 de setembro, 3165, Curitiba, PR 80230901, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paulo C.","family":"Stadzisz","sequence":"additional","affiliation":[{"name":"Graduate School in Electrical Engineering and Industrial Computer Science (CPGEI), Graduate School of Applied Computing (PPGCA, DAINF, DAELN), Federal University of Technology \u2014 Paran\u00e1 (UTFPR), Av. 7 de setembro, 3165, Curitiba, PR 80230901, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carlos R.","family":"Erig Lima","sequence":"additional","affiliation":[{"name":"Graduate School in Electrical Engineering and Industrial Computer Science (CPGEI), Graduate School of Applied Computing (PPGCA, DAINF, DAELN), Federal University of Technology \u2014 Paran\u00e1 (UTFPR), Av. 7 de setembro, 3165, Curitiba, PR 80230901, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2018,4,12]]},"reference":[{"key":"S0218126618501244BIB001","doi-asserted-by":"publisher","DOI":"10.1142\/S1793962310000031"},{"key":"S0218126618501244BIB002","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126605002611"},{"key":"S0218126618501244BIB004","doi-asserted-by":"publisher","DOI":"10.1145\/1941487.1941507"},{"key":"S0218126618501244BIB005","first-page":"1","volume":"35","author":"Nane R.","year":"2015","journal-title":"Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"S0218126618501244BIB006","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-012-9096-8"},{"key":"S0218126618501244BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2399275"},{"key":"S0218126618501244BIB016","doi-asserted-by":"publisher","DOI":"10.1109\/TSMCA.2008.2006371"},{"key":"S0218126618501244BIB019","doi-asserted-by":"publisher","DOI":"10.1109\/TLA.2015.7112020"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126618501244","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T22:17:42Z","timestamp":1565129862000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126618501244"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4,12]]},"references-count":8,"journal-issue":{"issue":"08","published-online":{"date-parts":[[2018,4,12]]},"published-print":{"date-parts":[[2018,7]]}},"alternative-id":["10.1142\/S0218126618501244"],"URL":"https:\/\/doi.org\/10.1142\/s0218126618501244","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,4,12]]}}}