{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T19:06:24Z","timestamp":1761419184462},"reference-count":8,"publisher":"World Scientific Pub Co Pte Lt","issue":"08","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,7]]},"abstract":"<jats:p> This paper exploits the CMOS beta multiplier circuit to synthesize a temperature-independent voltage reference suitable for low voltage and ultra-low power biomedical applications. The technique presented here uses only MOS transistors to generate Proportional To Absolute Temperature (PTAT) and Complimentary To Absolute Temperature (CTAT) currents. A self-biasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65[Formula: see text]nm CMOS has been developed and occupies 0.0039[Formula: see text]mm<jats:sup>2<\/jats:sup>, and at room temperature, it generates a 204[Formula: see text]mV reference voltage with 1.3[Formula: see text]mV drift over a wide temperature range (from [Formula: see text]40[Formula: see text]C to 125[Formula: see text]C). This has been designed to operate with a power supply voltage down to 0.6[Formula: see text]V and consumes 1.8[Formula: see text]uA current from the supply. The simulated temperature coefficient is 40[Formula: see text]ppm\/[Formula: see text]C. <\/jats:p>","DOI":"10.1142\/s0218126618501281","type":"journal-article","created":{"date-parts":[[2017,11,26]],"date-time":"2017-11-26T21:39:29Z","timestamp":1511732369000},"page":"1850128","source":"Crossref","is-referenced-by-count":24,"title":["A 0.6 V MOS-Only Voltage Reference for Biomedical Applications with 40 ppm\/\u2218C Temperature Drift"],"prefix":"10.1142","volume":"27","author":[{"given":"R.","family":"Nagulapalli","sequence":"first","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Oxford, OX33 1HX, UK"}]},{"given":"K.","family":"Hayatleh","sequence":"additional","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Oxford, OX33 1HX, UK"}]},{"given":"Steve","family":"Barker","sequence":"additional","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Oxford, OX33 1HX, UK"}]},{"given":"Sumathi","family":"Raparthy","sequence":"additional","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Oxford, OX33 1HX, UK"}]},{"given":"Nabil","family":"Yassine","sequence":"additional","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Oxford, OX33 1HX, UK"}]},{"given":"John","family":"Lidgey","sequence":"additional","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Oxford, OX33 1HX, UK"}]}],"member":"219","published-online":{"date-parts":[[2018,4,12]]},"reference":[{"key":"S0218126618501281BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/4.760378"},{"key":"S0218126618501281BIB003","doi-asserted-by":"publisher","DOI":"10.1049\/el:20050316"},{"key":"S0218126618501281BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/81.933328"},{"key":"S0218126618501281BIB007","first-page":"179","volume-title":"Analog Integrated Circuits and Signal Processing","volume":"27","author":"Palmisano G.","year":"2001"},{"key":"S0218126618501281BIB009","volume-title":"Sub-Threshold Design for Ultra Low-Power Systems","author":"Wang A.","year":"2006"},{"key":"S0218126618501281BIB010","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"S0218126618501281BIB011","volume-title":"Dynamic Offset Compensated CMOS Amplifiers","author":"Witte F.","year":"2010"},{"key":"S0218126618501281BIB012","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.905236"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126618501281","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T22:17:48Z","timestamp":1565129868000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126618501281"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4,12]]},"references-count":8,"journal-issue":{"issue":"08","published-online":{"date-parts":[[2018,4,12]]},"published-print":{"date-parts":[[2018,7]]}},"alternative-id":["10.1142\/S0218126618501281"],"URL":"https:\/\/doi.org\/10.1142\/s0218126618501281","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,4,12]]}}}