{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:38:18Z","timestamp":1740116298836,"version":"3.37.3"},"reference-count":6,"publisher":"World Scientific Pub Co Pte Ltd","issue":"13","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,12,15]]},"abstract":"<jats:p> A system-level correction successive approximation register analog-to-digital converter (SAR ADC) with regulated comparator of noise-tolerant technique is proposed. First, a substrate voltage boost technique is provided to improve the linearity and speed of sampling switch. Secondly, the proposed SAR ADC provides a comparator of noise regulation without redundant comparison cycle. The proposed comparator would be regulated in high-speed large noise state in large input differential signals. In the condition of small input differential signals, the comparator would be adjusted to low-speed small noise state. Furthermore, a high-speed low-power technique is proposed to optimize the performance of dynamic comparator. Additionally, a fast SAR logic structure is provided to increase the conversion speed of SAR ADC. To demonstrate the proposed techniques, a design example of SAR ADC is fabricated in 65[Formula: see text]nm CMOS technology. The SAR ADC is able to tolerate about 1.1\u00a0LSB noise errors in post-simulation with the operation state regulated automatically. The core occupies an active area of only 0.025[Formula: see text]mm<jats:sup>2<\/jats:sup> and consumes 1.5[Formula: see text]mW. Measurement results achieve SFDR [Formula: see text][Formula: see text]dB and SNDR [Formula: see text][Formula: see text]dB, resulting in the FOM of 21.6[Formula: see text]fJ per conversion step. <\/jats:p>","DOI":"10.1142\/s021812661850202x","type":"journal-article","created":{"date-parts":[[2018,3,16]],"date-time":"2018-03-16T02:20:52Z","timestamp":1521166852000},"page":"1850202","source":"Crossref","is-referenced-by-count":4,"title":["A System-Level Correction SAR ADC with Noise-Tolerant Technique"],"prefix":"10.1142","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1461-599X","authenticated-orcid":false,"given":"Daiguo","family":"Xu","sequence":"first","affiliation":[{"name":"School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu 611731, P. R. China"},{"name":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, P. R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaikai","family":"Xu","sequence":"additional","affiliation":[{"name":"School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu 611731, P. R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shiliu","family":"Xu","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, P. R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lu","family":"Liu","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, P. R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tao","family":"Liu","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, P. R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2018,8,3]]},"reference":[{"doi-asserted-by":"publisher","key":"S021812661850202XBIB004","DOI":"10.1109\/JSSC.2015.2413850"},{"doi-asserted-by":"publisher","key":"S021812661850202XBIB006","DOI":"10.1109\/JSSC.2014.2362851"},{"key":"S021812661850202XBIB009","first-page":"1053","volume":"62","author":"Palani R. K.","year":"2015","journal-title":"IEEE Trans. Circ. Syst. II"},{"doi-asserted-by":"publisher","key":"S021812661850202XBIB011","DOI":"10.1007\/s10470-015-0543-x"},{"doi-asserted-by":"publisher","key":"S021812661850202XBIB012","DOI":"10.1049\/el.2015.2796"},{"doi-asserted-by":"publisher","key":"S021812661850202XBIB013","DOI":"10.1109\/TVLSI.2016.2532605"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S021812661850202X","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T17:51:12Z","timestamp":1565113872000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S021812661850202X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,8,3]]},"references-count":6,"journal-issue":{"issue":"13","published-online":{"date-parts":[[2018,8,3]]},"published-print":{"date-parts":[[2018,12,15]]}},"alternative-id":["10.1142\/S021812661850202X"],"URL":"https:\/\/doi.org\/10.1142\/s021812661850202x","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2018,8,3]]}}}