{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:38:11Z","timestamp":1740116291391,"version":"3.37.3"},"reference-count":19,"publisher":"World Scientific Pub Co Pte Ltd","issue":"14","funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","award":["106-2221-E-011-152-MY3"],"award-info":[{"award-number":["106-2221-E-011-152-MY3"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,12,31]]},"abstract":"<jats:p> This paper presents the VLSI architecture of a low-latency and high-throughput sorted-QR decomposition (SQRD) engine for multiple-input multiple-output (MIMO) communication systems. In order to achieve a high processing throughput, the proposed design is architected based on a novel pipelined Givens rotation (GR) structure comprising of multi-dimension COordinate rotation DIgital computer (CORDIC) (MD-CORDIC) processing elements (PEs). Moreover, this design delivers the vector norm and conducts the sorting operation as a by-product of the vectoring operation on the execution flow of the CORDIC process. Therefore, excessive overheads for norm-calculation and sorting are excluded, and thus the latency is greatly reduced and throughput is enhanced. In addition, the proposed SQRD engine is operating directly on the complex-valued channel matrix to avoid the matrix augmentation caused by the real-valued decomposition of the channel matrix. This design has been synthesized, placed and routed, and the post-layout estimation results have shown that the processing throughput of the proposed SQRD architecture achieves an approximately 2[Formula: see text] improvement compared to the prior arts. <\/jats:p>","DOI":"10.1142\/s0218126618502201","type":"journal-article","created":{"date-parts":[[2018,3,14]],"date-time":"2018-03-14T04:18:08Z","timestamp":1521001088000},"page":"1850220","source":"Crossref","is-referenced-by-count":1,"title":["Architectural Optimizations for a High-Throughput Sorted QR Decomposition Circuit in MIMO Communication Systems"],"prefix":"10.1142","volume":"27","author":[{"given":"Wei-Yang","family":"Chen","sequence":"first","affiliation":[{"name":"National Taiwan University of Science and Technology, No. 43, Sec. 4, Keelung Road, Da\u2019an District, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0628-5129","authenticated-orcid":false,"given":"Chung-An","family":"Shen","sequence":"additional","affiliation":[{"name":"National Taiwan University of Science and Technology, No. 43, Sec. 4, Keelung Road, Da\u2019an District, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2018,8,23]]},"reference":[{"key":"S0218126618502201BIB001","doi-asserted-by":"publisher","DOI":"10.1109\/MWC.2010.5490974"},{"key":"S0218126618502201BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.2003.809458"},{"journal-title":"J. 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