{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,19]],"date-time":"2025-10-19T16:00:19Z","timestamp":1760889619254},"reference-count":21,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2019,2]]},"abstract":"<jats:p> A factor graph (FG) can be considered as a unified model combining a Bayesian network (BN) and a Markov random field (MRF). The inference mechanism of a FG can be used to perform reasoning under incompleteness and uncertainty, which is a challenging task in many intelligent systems and robotics. Unfortunately, a complete inference mechanism requires intense computations that introduces a long delay for the reasoning process to complete. Furthermore, in an energy-constrained system such as a mobile robot, it is required to have a very efficient inference process. In this paper, we present an embedded FG inference engine that employs a neural-inspired discretization mechanism. The engine runs on a system-on-chip (SoC) and is accelerated by its FPGA. We optimized our design to balance the trade-off between speed and hardware resource utilization. In our fully-optimized design, it can accelerate the inference process eight times faster than the normal execution, which is twice the speed-up gain achieved by a parallelized FG running on a PC. The experiments demonstrate that our design can be extended into an efficient reconfigurable computing machine. <\/jats:p>","DOI":"10.1142\/s0218126619500312","type":"journal-article","created":{"date-parts":[[2018,5,3]],"date-time":"2018-05-03T10:13:16Z","timestamp":1525342396000},"page":"1950031","source":"Crossref","is-referenced-by-count":7,"title":["FPGA-Based Hardware Accelerator for an Embedded Factor Graph with Configurable Optimization"],"prefix":"10.1142","volume":"28","author":[{"given":"Indar","family":"Sugiarto","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Petra Christian University, Jl. Siwalankerto 121-131, Surabaya 60234, Indonesia"},{"name":"Advanced Processor Technology, School of Computer Science, University of Manchester, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cristian","family":"Axenie","sequence":"additional","affiliation":[{"name":"Neuroscientific System Theory, Karlstra\u00dfe 45, 5. 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