{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:38:13Z","timestamp":1740116293710,"version":"3.37.3"},"reference-count":11,"publisher":"World Scientific Pub Co Pte Ltd","issue":"06","funder":[{"DOI":"10.13039\/501100001809","name":"the National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["61404022"],"award-info":[{"award-number":["61404022"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Science and Technology on Analog Integrated Circuit Laboratory Foundation","award":["0C09YJTJ1603"],"award-info":[{"award-number":["0C09YJTJ1603"]}]},{"DOI":"10.13039\/501100001809","name":"the National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["61774028"],"award-info":[{"award-number":["61774028"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"the Fundamental Research Funds for the China Central Universities","award":["ZYGX2016Z007"],"award-info":[{"award-number":["ZYGX2016Z007"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2019,6,15]]},"abstract":"<jats:p> In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7[Formula: see text]dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration. <\/jats:p>","DOI":"10.1142\/s0218126619500907","type":"journal-article","created":{"date-parts":[[2018,6,24]],"date-time":"2018-06-24T23:25:41Z","timestamp":1529882741000},"page":"1950090","source":"Crossref","is-referenced-by-count":0,"title":["A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters"],"prefix":"10.1142","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6738-7199","authenticated-orcid":false,"given":"Jian","family":"Luo","sequence":"first","affiliation":[{"name":"The State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Shahe Campus: No. 4, Section 2, North Jianshe Road, 610054, Chengdu, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jing","family":"Li","sequence":"additional","affiliation":[{"name":"The State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Shahe Campus: No. 4, Section 2, North Jianshe Road, 610054, Chengdu, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuangyi","family":"Wu","sequence":"additional","affiliation":[{"name":"The State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Shahe Campus: No. 4, Section 2, North Jianshe Road, 610054, Chengdu, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ning","family":"Ning","sequence":"additional","affiliation":[{"name":"The State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Shahe Campus: No. 4, Section 2, North Jianshe Road, 610054, Chengdu, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yang","family":"Liu","sequence":"additional","affiliation":[{"name":"The State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Shahe Campus: No. 4, Section 2, North Jianshe Road, 610054, Chengdu, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2019,6,12]]},"reference":[{"key":"S0218126619500907BIB002","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2010.08.014"},{"key":"S0218126619500907BIB003","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-015-0177-3"},{"key":"S0218126619500907BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/JSTSP.2009.2020269"},{"key":"S0218126619500907BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2530819"},{"key":"S0218126619500907BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.882224"},{"key":"S0218126619500907BIB011","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.377922"},{"key":"S0218126619500907BIB012","first-page":"1","volume-title":"IEEE Custom Integrated Circuits Conf.","author":"Fang J.","year":"2015"},{"key":"S0218126619500907BIB016","first-page":"466","volume-title":"IEEE Int. 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