{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,8]],"date-time":"2025-09-08T06:34:01Z","timestamp":1757313241159,"version":"3.37.3"},"reference-count":25,"publisher":"World Scientific Pub Co Pte Ltd","issue":"08","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2019,7]]},"abstract":"<jats:p> This paper presents a novel current mirror structure based on level shifted class-AB flipped voltage follower cell, which operates at the supply voltage of 1.2[Formula: see text]V. The level shifted class-AB flipped voltage follower cell and regulated cascode structure are used at the input and the output stages to achieve low input resistance and very high output resistance, respectively. A comparison of performance parameters of the proposed current mirror with existing structures shows that the proposed current mirror has a very less current tracking error of 0.99%, high output resistance of 18.7[Formula: see text]M[Formula: see text], wide bandwidth of 239.245[Formula: see text]MHz and low power dissipation of 104[Formula: see text][Formula: see text]W. The proposed circuit has been simulated in Cadence virtuoso analog design environment and layout of the proposed circuit has been designed in Cadence virtuoso layout XL editor using BSIM3V3 180[Formula: see text]nm CMOS technology. The post-layout simulation results have also been presented to demonstrate the effectiveness of the proposed circuit. <\/jats:p>","DOI":"10.1142\/s0218126619501408","type":"journal-article","created":{"date-parts":[[2018,9,6]],"date-time":"2018-09-06T23:47:11Z","timestamp":1536277631000},"page":"1950140","source":"Crossref","is-referenced-by-count":10,"title":["High Performance CMOS Current Mirror Using Class-AB Level Shifted Bulk Driven Flipped Voltage Follower Cell"],"prefix":"10.1142","volume":"28","author":[{"family":"Caffey","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, Punjab, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1369-7073","authenticated-orcid":false,"given":"Rishikesh","family":"Pandey","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, Punjab, India"}]}],"member":"219","published-online":{"date-parts":[[2019,7,29]]},"reference":[{"volume-title":"Analogue IC Design: The Current Mode Approach","year":"1990","author":"Toumazou C.","key":"S0218126619501408BIB001"},{"key":"S0218126619501408BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/4.50316"},{"key":"S0218126619501408BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/4.58292"},{"key":"S0218126619501408BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/81.295247"},{"key":"S0218126619501408BIB005","doi-asserted-by":"publisher","DOI":"10.1080\/00207210902876487"},{"key":"S0218126619501408BIB006","doi-asserted-by":"publisher","DOI":"10.1049\/el:20021062"},{"volume-title":"Analysis and Design of Analog Integrated Circuits","year":"2001","author":"Gray P.","key":"S0218126619501408BIB007"},{"key":"S0218126619501408BIB008","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20010441"},{"key":"S0218126619501408BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.822429"},{"key":"S0218126619501408BIB010","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCS.2007.4292650"},{"key":"S0218126619501408BIB011","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-22543-7_51"},{"key":"S0218126619501408BIB012","doi-asserted-by":"publisher","DOI":"10.1002\/cta.617"},{"key":"S0218126619501408BIB013","doi-asserted-by":"publisher","DOI":"10.1002\/cta.618"},{"key":"S0218126619501408BIB014","doi-asserted-by":"publisher","DOI":"10.1109\/CICN.2011.9"},{"key":"S0218126619501408BIB015","doi-asserted-by":"publisher","DOI":"10.1109\/MSPCT.2013.6782129"},{"key":"S0218126619501408BIB016","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2012.12.006"},{"key":"S0218126619501408BIB017","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2016.7803943"},{"key":"S0218126619501408BIB018","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126617501808"},{"key":"S0218126619501408BIB019","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2002.1010299"},{"key":"S0218126619501408BIB020","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-012-9864-1"},{"key":"S0218126619501408BIB022","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2017.0305"},{"key":"S0218126619501408BIB023","unstructured":"B. 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