{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:37:51Z","timestamp":1740116271872,"version":"3.37.3"},"reference-count":43,"publisher":"World Scientific Pub Co Pte Ltd","issue":"01","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2020,1]]},"abstract":"<jats:p> A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[Formula: see text]mV and 20[Formula: see text]MHz clock frequency for 1[Formula: see text]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[Formula: see text]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[Formula: see text][Formula: see text]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[Formula: see text]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [Formula: see text][Formula: see text][Formula: see text]m for TBCCCP, [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP2 and [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP4. <\/jats:p>","DOI":"10.1142\/s0218126620500139","type":"journal-article","created":{"date-parts":[[2019,2,13]],"date-time":"2019-02-13T01:32:25Z","timestamp":1550021545000},"page":"2050013","source":"Crossref","is-referenced-by-count":0,"title":["Fast-Transient-Response Low-Voltage Integrated, Interleaved DC\u2013DC Converter for Implantable Devices"],"prefix":"10.1142","volume":"29","author":[{"given":"Najmeh Cheraghi","family":"Shirazi","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6944-699X","authenticated-orcid":false,"given":"Abumoslem","family":"Jannesari","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Tarbiat Modares University, Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pooya","family":"Torkzadeh","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2019,3,19]]},"reference":[{"key":"S0218126620500139BIB001","doi-asserted-by":"publisher","DOI":"10.1016\/j.sna.2016.06.040"},{"key":"S0218126620500139BIB002","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-47587-5"},{"key":"S0218126620500139BIB003","first-page":"1","volume-title":"2010 IEEE Custom Integrated Circuits Conf. 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