{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:38:06Z","timestamp":1740116286680,"version":"3.37.3"},"reference-count":27,"publisher":"World Scientific Pub Co Pte Ltd","issue":"04","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2020,3,31]]},"abstract":"<jats:p> The lifetime reliability of processors has become a major design constraint in the dark silicon era. Processor reliability issues are mainly due to design defects and aging. Unlike design defects, however, aging faults gradually accumulate over time. Many methods have recently been proposed to monitor the performance degradation of circuits. In this study, an architectural solution that extends the circuit-level age monitoring to processor stages is proposed for monitoring performance degradation. When degradation of a stage quantified as delay of half of the reference clock occurs, a self-repairing mechanism is triggered. This mechanism configures an field programmable gate array (FPGA), which takes over the functions of the degraded unit. The proposed self-repairing mechanism is applied to the stages of the processor data-path. This method (SeRA) has lesser area overhead compared with the state-of-art solutions. <\/jats:p>","DOI":"10.1142\/s021812662050053x","type":"journal-article","created":{"date-parts":[[2019,4,22]],"date-time":"2019-04-22T06:11:13Z","timestamp":1555913473000},"page":"2050053","source":"Crossref","is-referenced-by-count":0,"title":["SeRA: Self-Repairing Architecture for Dark Silicon Era"],"prefix":"10.1142","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2192-8153","authenticated-orcid":false,"given":"Harini","family":"sriraman","sequence":"first","affiliation":[{"name":"School of Computing Science and Engineering, Vellore Institute of Technology, Chennai, Tamil Nadu, India"}]},{"given":"Pattabiraman","family":"Venkatasubbu","sequence":"additional","affiliation":[{"name":"School of Computing Science and Engineering, Vellore Institute of Technology, Chennai, Tamil Nadu, India"}]}],"member":"219","published-online":{"date-parts":[[2019,6,13]]},"reference":[{"key":"S021812662050053XBIB001","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.58"},{"key":"S021812662050053XBIB002","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2014.6783381"},{"key":"S021812662050053XBIB003","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2017.2735383"},{"key":"S021812662050053XBIB004","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4471-5058-9_223"},{"volume-title":"Computer Architecture: A Quantitative Approach","year":"2011","author":"Hennessy J. L.","key":"S021812662050053XBIB005"},{"key":"S021812662050053XBIB007","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2601959"},{"key":"S021812662050053XBIB008","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-7909-3_27"},{"first-page":"163","volume-title":"2015 IEEE 24th Asian Test Symp. (ATS)","author":"Gupta S.","key":"S021812662050053XBIB009"},{"key":"S021812662050053XBIB010","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591600"},{"key":"S021812662050053XBIB011","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2747938"},{"key":"S021812662050053XBIB012","doi-asserted-by":"publisher","DOI":"10.1145\/3107615"},{"key":"S021812662050053XBIB013","doi-asserted-by":"publisher","DOI":"10.1145\/2501654.2501662"},{"key":"S021812662050053XBIB014","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771786"},{"key":"S021812662050053XBIB015","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2014.2"},{"key":"S021812662050053XBIB016","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"S021812662050053XBIB017","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2114681"},{"volume-title":"Post-Silicon and Runtime Verification for Modern Processors","year":"2010","author":"Wagner I.","key":"S021812662050053XBIB018"},{"key":"S021812662050053XBIB019","first-page":"1","volume-title":"ACM Proc. 51st Annual Design Automation Conf.","author":"Shafique M.","year":"2015"},{"key":"S021812662050053XBIB021","doi-asserted-by":"publisher","DOI":"10.1007\/s10586-014-0401-0"},{"key":"S021812662050053XBIB022","doi-asserted-by":"publisher","DOI":"10.1145\/2700104"},{"key":"S021812662050053XBIB023","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-10-7871-2_45"},{"key":"S021812662050053XBIB024","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2015.01.001"},{"key":"S021812662050053XBIB025","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-018-2238-4"},{"key":"S021812662050053XBIB026","doi-asserted-by":"publisher","DOI":"10.1145\/2694730.2694732"},{"key":"S021812662050053XBIB027","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-02465-9_51"},{"key":"S021812662050053XBIB028","doi-asserted-by":"publisher","DOI":"10.1145\/2856125"},{"key":"S021812662050053XBIB029","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2014.1"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S021812662050053X","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,5,11]],"date-time":"2020-05-11T10:11:36Z","timestamp":1589191896000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S021812662050053X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6,13]]},"references-count":27,"journal-issue":{"issue":"04","published-print":{"date-parts":[[2020,3,31]]}},"alternative-id":["10.1142\/S021812662050053X"],"URL":"https:\/\/doi.org\/10.1142\/s021812662050053x","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2019,6,13]]}}}