{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:51:23Z","timestamp":1761648683614,"version":"3.37.3"},"reference-count":16,"publisher":"World Scientific Pub Co Pte Ltd","issue":"06","funder":[{"name":"the Ministry of Science and Technology under the Grants","award":["MOST 108-2218-E-110-002-","MOST 107-2218-E-110-016-"],"award-info":[{"award-number":["MOST 108-2218-E-110-002-","MOST 107-2218-E-110-016-"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2020,5]]},"abstract":"<jats:p> A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low-[Formula: see text] PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power\u2013delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate. <\/jats:p>","DOI":"10.1142\/s0218126620500954","type":"journal-article","created":{"date-parts":[[2019,7,18]],"date-time":"2019-07-18T04:17:36Z","timestamp":1563423456000},"page":"2050095","source":"Crossref","is-referenced-by-count":6,"title":["A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry"],"prefix":"10.1142","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2426-2879","authenticated-orcid":false,"given":"Chua-Chin","family":"Wang","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, National Sun Yat-Sen University, No. 70 Lian-Hai Road, Kaohsiung 80424, Taiwan, R. O. P. R. China"}]},{"given":"Zong-You","family":"Hou","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Sun Yat-Sen University, No. 70 Lian-Hai Road, Kaohsiung 80424, Taiwan, R. O. P. R. China"}]},{"given":"Deng-Shian","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Sun Yat-Sen University, No. 70 Lian-Hai Road, Kaohsiung 80424, Taiwan, R. O. P. R. China"}]},{"given":"Chia-Lung","family":"Hsieh","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Sun Yat-Sen University, No. 70 Lian-Hai Road, Kaohsiung 80424, Taiwan, R. O. P. R. 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