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Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25\u201350\u00a0dB gain, and post-layout simulations showed a 15[Formula: see text]dB reduction in the harmonic distortion for 20[Formula: see text]mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108[Formula: see text][Formula: see text]m<jats:sup>2<\/jats:sup> silicon area and consumes 0.43\u00a0[Formula: see text]A from a 1.2[Formula: see text]V power supply. <\/jats:p>","DOI":"10.1142\/s0218126620501133","type":"journal-article","created":{"date-parts":[[2019,8,21]],"date-time":"2019-08-21T03:07:49Z","timestamp":1566356869000},"page":"2050113","source":"Crossref","is-referenced-by-count":2,"title":["A VGA Linearity Improvement Technique for ECG Analog Front-End in 65nm CMOS"],"prefix":"10.1142","volume":"29","author":[{"given":"Rajasekhar","family":"Nagulapalli","sequence":"first","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Wheatley, Oxford, OX33 1HX, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0149-1772","authenticated-orcid":false,"given":"Khaled","family":"Hayatleh","sequence":"additional","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Wheatley, Oxford, OX33 1HX, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steve","family":"Barker","sequence":"additional","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Wheatley, Oxford, OX33 1HX, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2019,9,20]]},"reference":[{"key":"S0218126620501133BIB001","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2349994"},{"key":"S0218126620501133BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/ICRAECT.2017.17"},{"key":"S0218126620501133BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/ICECCT.2017.8117953"},{"key":"S0218126620501133BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.811979"},{"key":"S0218126620501133BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCNT.2018.8493494"},{"key":"S0218126620501133BIB006","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-018-1148-y"},{"key":"S0218126620501133BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2011.2163404"},{"key":"S0218126620501133BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/ICMDCS.2017.8211724"},{"key":"S0218126620501133BIB009","doi-asserted-by":"publisher","DOI":"10.1007\/0-387-25747-0_4"},{"key":"S0218126620501133BIB010","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCNT.2018.8493494"},{"key":"S0218126620501133BIB011","volume-title":"Analog Integrated Circuit Design","author":"Carusone T. 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