{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,11]],"date-time":"2025-06-11T17:03:15Z","timestamp":1749661395199,"version":"3.37.3"},"reference-count":24,"publisher":"World Scientific Pub Co Pte Ltd","issue":"09","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2020,7]]},"abstract":"<jats:p> Dedicated hardware for \u201cDiscrete Wavelet Transform\u201d (DWT) is at high demand for real-time imaging operations in any standalone electronic devices, as DWT is being extensively utilized for most of the transform-domain imagery applications. Various DWT algorithms exist in the literature facilitating its software implementations which are generally unsuitable for real-time imaging in any stand-alone devices due to their power intensiveness and huge computation time. In this paper, a convolutional DWT-based pipelined and tunable VLSI architecture of Daubechies 9\/7 and 5\/3 DWT filter is presented. Our proposed architecture, which mingles the advantages of convolutional and lifting DWT while discarding their notable disadvantages, is made area and memory efficient by exploiting \u201cDistributed Arithmetic\u2019 (DA) in our own ingenious way. Almost 90% reduction in the memory size than other notable architectures is reported. In our proposed architecture, both the 9\/7 and 5\/3 DWT filters can be realized with a selection input, \u201cmode\u201d. With the introduction of DA, pipelining and parallelism are easily incorporated into our proposed 1D\/2D DWT architectures. The area requirement and critical path delay are reduced to almost 38.3% and 50% than that of the latest remarkable designs. The performance of the proposed VLSI architecture also excels in real-time applications. <\/jats:p>","DOI":"10.1142\/s0218126620501510","type":"journal-article","created":{"date-parts":[[2019,10,14]],"date-time":"2019-10-14T03:49:53Z","timestamp":1571024993000},"page":"2050151","source":"Crossref","is-referenced-by-count":3,"title":["A Memory Efficient, Multiplierless &amp; Modular VLSI Architecture of 1D\/2D Re-Configurable 9\/7 &amp; 5\/3 DWT Filters Using Distributed Arithmetic"],"prefix":"10.1142","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4398-0777","authenticated-orcid":false,"given":"Anirban","family":"Chakraborty","sequence":"first","affiliation":[{"name":"Electronics and Telecommunication Engineering Department, Indian Institute of Engineering Science and Technology, Shibpur, Howrah, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ayan","family":"Banerjee","sequence":"additional","affiliation":[{"name":"Electronics and Telecommunication Engineering Department, Indian Institute of Engineering Science and Technology, Shibpur, Howrah, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2020,2,5]]},"reference":[{"volume-title":"Wavelets: Algorithms and Applications","year":"1993","author":"Meyer Y.","key":"S0218126620501510BIB001"},{"key":"S0218126620501510BIB002","doi-asserted-by":"publisher","DOI":"10.1007\/BF02476026"},{"key":"S0218126620501510BIB003","first-page":"529","volume-title":"ISCAS 2001. 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