{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T15:06:09Z","timestamp":1761663969815,"version":"3.37.3"},"reference-count":24,"publisher":"World Scientific Pub Co Pte Ltd","issue":"10","funder":[{"name":"graduate student innovation plan of Jiangsu Province fund","award":["201710324001Y"],"award-info":[{"award-number":["201710324001Y"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2020,8]]},"abstract":"<jats:p> This paper presents a scheme for the modified chaotic circuits based on inductance integration. In view of the fact that the DC resistance of an inductor in the circuit cannot be ignored, this way of constructing the circuits is provided that can eliminate its influence on the integral circuits. By means of cascading an inverting adder circuit and inductance integral circuit, the output signal of the integral circuit is fed back to the inverting adder circuit, and its additive term is artificially added to match the actual inductance integrated circuit to achieve integral circuit based on the actual inductor which can offset the effect of its DC resistance. In order to verify the generality of the design, the process of designing Lorenz chaotic circuit is given and its attractors can also be observed from the oscilloscope. <\/jats:p>","DOI":"10.1142\/s0218126620501595","type":"journal-article","created":{"date-parts":[[2019,10,29]],"date-time":"2019-10-29T07:40:14Z","timestamp":1572334814000},"page":"2050159","source":"Crossref","is-referenced-by-count":3,"title":["A General Chaotic Circuit Design and Hardware Implementation via the Inductance Integrators"],"prefix":"10.1142","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3505-1428","authenticated-orcid":false,"given":"Wei","family":"Xu","sequence":"first","affiliation":[{"name":"College of Computer and Information, Hohai University, Fochengxi Road, Nanjing, Jiangsu, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ning","family":"Cao","sequence":"additional","affiliation":[{"name":"College of Computer and Information, Hohai University, Fochengxi Road, Nanjing, Jiangsu, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2019,12,16]]},"reference":[{"key":"S0218126620501595BIB001","doi-asserted-by":"publisher","DOI":"10.1142\/S0218127408020987"},{"key":"S0218126620501595BIB002","doi-asserted-by":"publisher","DOI":"10.1142\/S0218127407018087"},{"key":"S0218126620501595BIB003","doi-asserted-by":"publisher","DOI":"10.1007\/s11071-011-0238-5"},{"key":"S0218126620501595BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2435211"},{"key":"S0218126620501595BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1986.1085869"},{"key":"S0218126620501595BIB006","doi-asserted-by":"publisher","DOI":"10.1007\/s11071-017-3505-2"},{"volume-title":"A Route to Chaos Using FPGAs","year":"2012","author":"Bharathwaj M.","key":"S0218126620501595BIB007"},{"key":"S0218126620501595BIB008","doi-asserted-by":"publisher","DOI":"10.1049\/el:20000293"},{"key":"S0218126620501595BIB009","doi-asserted-by":"publisher","DOI":"10.1007\/s11071-017-3907-1"},{"key":"S0218126620501595BIB010","doi-asserted-by":"publisher","DOI":"10.1109\/IADCC.2015.7154811"},{"key":"S0218126620501595BIB011","first-page":"135-1","volume":"20","author":"Maximiliano A.","year":"2018","journal-title":"Entropy"},{"key":"S0218126620501595BIB012","first-page":"86","volume":"58","author":"S\u00e1nchez-L\u00f3pez C.","year":"2012","journal-title":"Rev. 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