{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:37:33Z","timestamp":1740116253773,"version":"3.37.3"},"reference-count":28,"publisher":"World Scientific Pub Co Pte Ltd","issue":"11","funder":[{"name":"the National Key Research and Development Program of China","award":["2018YFB2101300"],"award-info":[{"award-number":["2018YFB2101300"]}]},{"name":"Foundation of Shanghai Key Laboratory of Navigation and Location-Based Services","award":["0"],"award-info":[{"award-number":["0"]}]},{"name":"Open Project Program of the State Key Laboratory of Mathematical Engineering and Advanced Computing","award":["0"],"award-info":[{"award-number":["0"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2020,9,15]]},"abstract":"<jats:p> The explosive growth of video applications has produced great challenges for data storage and transmission. In this paper, we propose a new ROI (region of interest) encoding solution to accelerate the processing and reduce the bitrate based on the latest video compression standard H.265\/HEVC (High-Efficiency Video Coding). The traditional ROI extraction mapping algorithm uses pixel-based Gaussian background modeling (GBM), which requires a large number of complex floating-point calculations. Instead, we propose a block-based GBM to set up the background, which is in accord with the block division of HEVC. Then, we use the SAD (sum of absolute difference) rule to separate the foreground block from the background block, and these blocks are mapped into the coding tree unit (CTU) of HEVC. Moreover, the quantization parameter (QP) is adjusted according to the distortion rate automatically. The experimental results show that the processing speed on FPGA has reached a real-time level of 22 FPS (frames per second) for full high-definition videos ([Formula: see text]), and the bitrate is reduced by 10% on average with stable video quality. <\/jats:p>","DOI":"10.1142\/s0218126620501820","type":"journal-article","created":{"date-parts":[[2019,12,9]],"date-time":"2019-12-09T06:59:45Z","timestamp":1575874785000},"page":"2050182","source":"Crossref","is-referenced-by-count":4,"title":["FPGA-Based ROI Encoding for HEVC Video Bitrate Reduction"],"prefix":"10.1142","volume":"29","author":[{"given":"Zhilei","family":"Chai","sequence":"first","affiliation":[{"name":"School of IoT Engineering, Jiangnan University, Wuxi, Jiangsu 214122, P. R. China"}]},{"given":"Shen","family":"Li","sequence":"additional","affiliation":[{"name":"School of IoT Engineering, Jiangnan University, Wuxi, Jiangsu 214122, P. R. China"}]},{"given":"Qunfang","family":"He","sequence":"additional","affiliation":[{"name":"MoE Engineering Research Center for Software\/Hardware Co-Design Technology, East China Normal University, North Zhongshan Road Campus, Shanghai 200062, P. R. China"}]},{"given":"Mingsong","family":"Chen","sequence":"additional","affiliation":[{"name":"MoE Engineering Research Center for Software\/Hardware Co-Design Technology, East China Normal University, North Zhongshan Road Campus, Shanghai 200062, P. R. China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0512-8049","authenticated-orcid":false,"given":"Wenjie","family":"Chen","sequence":"additional","affiliation":[{"name":"MoE Engineering Research Center for Software\/Hardware Co-Design Technology, East China Normal University, North Zhongshan Road Campus, Shanghai 200062, P. R. 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