{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T19:09:31Z","timestamp":1761419371354,"version":"3.40.5"},"reference-count":21,"publisher":"World Scientific Pub Co Pte Ltd","issue":"14","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2020,11]]},"abstract":"<jats:p> A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65[Formula: see text]nm CMOS technology. It results in 81[Formula: see text]dB voltage gain, which is 21[Formula: see text]dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8[Formula: see text]V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1[Formula: see text]V supply. The circuit draws a total static current of 295[Formula: see text][Formula: see text]A and occupies 5000[Formula: see text][Formula: see text]m<jats:sup>2<\/jats:sup> of silicon area. <\/jats:p>","DOI":"10.1142\/s0218126620502205","type":"journal-article","created":{"date-parts":[[2020,2,13]],"date-time":"2020-02-13T07:59:46Z","timestamp":1581580786000},"page":"2050220","source":"Crossref","is-referenced-by-count":11,"title":["A Positive Feedback-Based Op-Amp Gain Enhancement Technique for High-Precision Applications"],"prefix":"10.1142","volume":"29","author":[{"given":"Rajasekhar","family":"Nagulapalli","sequence":"first","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Wheatley, Oxford, OX33 1HX, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0149-1772","authenticated-orcid":false,"given":"Khaled","family":"Hayatleh","sequence":"additional","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Wheatley, Oxford, OX33 1HX, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steve","family":"Barker","sequence":"additional","affiliation":[{"name":"School of Engineering, Computing and Mathematics, Oxford Brookes University, Wheatley Campus, Wheatley, Oxford, OX33 1HX, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2020,3,20]]},"reference":[{"key":"S0218126620502205BIB001","doi-asserted-by":"crossref","first-page":"730","DOI":"10.1109\/JSSC.2007.891666","volume":"42","author":"Wu P. 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