{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,4,18]],"date-time":"2023-04-18T06:16:07Z","timestamp":1681798567128},"reference-count":17,"publisher":"World Scientific Pub Co Pte Lt","issue":"05","funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61874156"],"award-info":[{"award-number":["61874156"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61904001"],"award-info":[{"award-number":["61904001"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61904047"],"award-info":[{"award-number":["61904047"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2021,4]]},"abstract":"<jats:p> As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption. <\/jats:p>","DOI":"10.1142\/s0218126621200036","type":"journal-article","created":{"date-parts":[[2020,7,24]],"date-time":"2020-07-24T12:35:50Z","timestamp":1595594150000},"page":"2120003","source":"Crossref","is-referenced-by-count":1,"title":["Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier"],"prefix":"10.1142","volume":"30","author":[{"given":"Zhengfeng","family":"Huang","sequence":"first","affiliation":[{"name":"School of Electronic Science & Applied Physics, Hefei University of Technology, 193 Tunxi Road, Hefei, Anhui 230009, P.\u00a0R.\u00a0China"}]},{"given":"Zian","family":"Su","sequence":"additional","affiliation":[{"name":"School of Electronic Science & Applied Physics, Hefei University of Technology, 193 Tunxi Road, Hefei, Anhui 230009, P.\u00a0R.\u00a0China"}]},{"given":"Tianming","family":"Ni","sequence":"additional","affiliation":[{"name":"College of Electrical Engineering, Anhui Polytechnic University, 8 Central Beijing Road, Wuhu, Anhui 241000, P.\u00a0R.\u00a0China"}]},{"given":"Qi","family":"Xu","sequence":"additional","affiliation":[{"name":"School of Electronic Science & Applied Physics, Hefei University of Technology, 193 Tunxi Road, Hefei, Anhui 230009, P.\u00a0R.\u00a0China"}]},{"given":"Haochen","family":"Qi","sequence":"additional","affiliation":[{"name":"School of Electronic Science & Applied Physics, Hefei University of Technology, 193 Tunxi Road, Hefei, Anhui 230009, P.\u00a0R.\u00a0China"}]},{"given":"Yingchun","family":"Lu","sequence":"additional","affiliation":[{"name":"School of Electronic Science & Applied Physics, Hefei University of Technology, 193 Tunxi Road, Hefei, Anhui 230009, P.\u00a0R.\u00a0China"}]},{"given":"Manzi","family":"Eric","sequence":"additional","affiliation":[{"name":"School of Computer Science and Engineering, Anhui University of Science and Technology, 168 Taifeng Street, Huainan, Anhui 232001, P.\u00a0R.\u00a0China"}]},{"given":"Hui","family":"Xu","sequence":"additional","affiliation":[{"name":"School of Computer Science and Engineering, Anhui University of Science and Technology, 168 Taifeng Street, Huainan, Anhui 232001, P.\u00a0R.\u00a0China"}]}],"member":"219","published-online":{"date-parts":[[2020,9,23]]},"reference":[{"key":"S0218126621200036BIB001","doi-asserted-by":"publisher","DOI":"10.1142\/S0129156404002430"},{"key":"S0218126621200036BIB003","doi-asserted-by":"publisher","DOI":"10.1142\/S0129156404002351"},{"key":"S0218126621200036BIB004","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715207"},{"key":"S0218126621200036BIB005","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2019.05.022"},{"key":"S0218126621200036BIB006","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126614500819"},{"key":"S0218126621200036BIB007","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126616501632"},{"key":"S0218126621200036BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"S0218126621200036BIB009","first-page":"2115","volume":"64","author":"Harrington C.","year":"2017","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"S0218126621200036BIB010","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2015.72"},{"key":"S0218126621200036BIB011","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-015-5551-3"},{"key":"S0218126621200036BIB012","doi-asserted-by":"publisher","DOI":"10.1109\/4.340421"},{"key":"S0218126621200036BIB013","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542315"},{"key":"S0218126621200036BIB014","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859586"},{"key":"S0218126621200036BIB015","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2006.379718"},{"key":"S0218126621200036BIB016","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2777788"},{"key":"S0218126621200036BIB017","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1982.4336490"},{"key":"S0218126621200036BIB018","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.4374"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126621200036","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,12]],"date-time":"2021-05-12T08:16:46Z","timestamp":1620807406000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126621200036"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,23]]},"references-count":17,"journal-issue":{"issue":"05","published-print":{"date-parts":[[2021,4]]}},"alternative-id":["10.1142\/S0218126621200036"],"URL":"https:\/\/doi.org\/10.1142\/s0218126621200036","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,9,23]]}}}