{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,4]],"date-time":"2025-09-04T13:50:13Z","timestamp":1756993813085,"version":"3.40.5"},"reference-count":28,"publisher":"World Scientific Pub Co Pte Ltd","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2021,3,15]]},"abstract":"<jats:p> This paper presents noise reduction and modified asynchronous logic regulation techniques used in successive approximation register (SAR) analog-to-digital converter (ADC). With a transconductance enhanced structure, noise reduction is provided in the dynamic comparator. The input referred noise of the proposed comparator is about 165[Formula: see text][Formula: see text]V rms at 60<jats:sup>\u2218<\/jats:sup>C (typical corner). An enhanced-positive-feedback loop is introduced to reduce the regeneration delay of the comparator. In addition, a modified asynchronous logic regulation technique is exhibited, a clock with adaptable delay is driving the comparator in approximation phase. Consequently, the settling accuracy of DAC (Digital-to-Analog Converter) is enough and the conversion speed of SAR ADC is increased without any redundant cycles. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 4[Formula: see text]mW from 1.2[Formula: see text]V power supply with a [Formula: see text][Formula: see text]dB and [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.048[Formula: see text]mm<jats:sup>2<\/jats:sup>, and the corresponding FoM is 27.2[Formula: see text]fJ\/conversion-step at Nyquist rate. <\/jats:p>","DOI":"10.1142\/s0218126621500407","type":"journal-article","created":{"date-parts":[[2020,5,31]],"date-time":"2020-05-31T02:16:35Z","timestamp":1590891395000},"page":"2150040","source":"Crossref","is-referenced-by-count":2,"title":["A Noise Reduction 12-bit 125-MSPS SAR ADC with Modified Asynchronous Logic Regulation Technique"],"prefix":"10.1142","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1461-599X","authenticated-orcid":false,"given":"Daiguo","family":"Xu","sequence":"first","affiliation":[{"name":"School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu 611731, P. R. China"},{"name":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, P. R. China"}]},{"given":"Han","family":"Yang","sequence":"additional","affiliation":[{"name":"Sichuan Solid State Circuit Research Institute, P. R. China"}]},{"given":"Xing","family":"Sheng","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, P. R. China"}]},{"given":"Ting","family":"Sun","sequence":"additional","affiliation":[{"name":"School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu 611731, P. R. China"}]},{"given":"Guangbing","family":"Chen","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, P. R. China"}]},{"given":"Shiliu","family":"Xu","sequence":"additional","affiliation":[{"name":"School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu 611731, P. R. China"}]},{"given":"Can","family":"Zhu","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, P. R. China"}]},{"given":"Jianan","family":"Wang","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, P. R. China"}]},{"given":"Dongbin","family":"Fu","sequence":"additional","affiliation":[{"name":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, P. R. China"}]}],"member":"219","published-online":{"date-parts":[[2020,8,8]]},"reference":[{"doi-asserted-by":"publisher","key":"S0218126621500407BIB002","DOI":"10.1109\/TCSII.2017.2756036"},{"doi-asserted-by":"publisher","key":"S0218126621500407BIB003","DOI":"10.1109\/TVLSI.2018.2846746"},{"issue":"7","key":"S0218126621500407BIB004","first-page":"1174","volume":"67","author":"Zhang J.","year":"2019","journal-title":"IEEE Trans. Circ. Syst. II Exp. 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