{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T11:58:43Z","timestamp":1648727923180},"reference-count":14,"publisher":"World Scientific Pub Co Pte Lt","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2021,3,15]]},"abstract":"<jats:p> Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software-Defined Radio (SDR) in a reasonable area. New issues can arise due to usage of DPR technique such as guaranteeing proper connections for the ports of the Reconfigurable Modules (RMs) which share the same Reconfigurable Region (RR) on the FPGA, waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. Also, the Clock Domain Crossing (CDC) verification of the dynamically reconfigurable systems is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. This paper summarizes our previous work to address these verification challenges for DPR. The approaches are demonstrated on a SDR system to show the effectiveness of applying these approaches in the design cycle. <\/jats:p>","DOI":"10.1142\/s0218126621500420","type":"journal-article","created":{"date-parts":[[2020,6,3]],"date-time":"2020-06-03T06:07:30Z","timestamp":1591164450000},"page":"2150042","source":"Crossref","is-referenced-by-count":0,"title":["Functional Verification of Dynamic Partial Reconfiguration for Software-Defined Radio"],"prefix":"10.1142","volume":"30","author":[{"given":"Islam","family":"Ahmed","sequence":"first","affiliation":[{"name":"IC Verification Solutions, Mentor Graphics, a Siemens Business, Cairo 11361, Egypt"}]},{"given":"Ahmed Nader","family":"Mohieldin","sequence":"additional","affiliation":[{"name":"Electronics and Communications Engineering Department, Cairo University, Giza 12613, Egypt"}]},{"given":"Hassan","family":"Mostafa","sequence":"additional","affiliation":[{"name":"University of Science and Technology, Nanotechnology and Nanoelectronics Program, Zewail City of Science and Technology, October Gardens, 6th of October, Giza 12578, Egypt"}]}],"member":"219","published-online":{"date-parts":[[2020,8,19]]},"reference":[{"key":"S0218126621500420BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2018.8368552"},{"key":"S0218126621500420BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2018.8624012"},{"key":"S0218126621500420BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2018.8623847"},{"key":"S0218126621500420BIB006","volume-title":"Proc. Synopsys User Group Meeting (SNUG)","author":"Cummings C.","year":"2008"},{"key":"S0218126621500420BIB007","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-46117-5_17"},{"key":"S0218126621500420BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/FDL.2008.4641421"},{"key":"S0218126621500420BIB009","doi-asserted-by":"publisher","DOI":"10.1145\/1297666.1297681"},{"key":"S0218126621500420BIB010","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.18"},{"key":"S0218126621500420BIB011","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2011.6132709"},{"key":"S0218126621500420BIB012","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145735"},{"key":"S0218126621500420BIB013","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090805"},{"key":"S0218126621500420BIB016","first-page":"498","volume-title":"Int. Conf. Electronics, Circuits, and Systems (ICECS)","author":"Sadek A.","year":"2015"},{"key":"S0218126621500420BIB017","doi-asserted-by":"publisher","DOI":"10.1002\/dac.3342"},{"key":"S0218126621500420BIB018","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2016.7843024"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126621500420","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,3,31]],"date-time":"2021-03-31T03:15:02Z","timestamp":1617160502000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126621500420"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8,19]]},"references-count":14,"journal-issue":{"issue":"03","published-print":{"date-parts":[[2021,3,15]]}},"alternative-id":["10.1142\/S0218126621500420"],"URL":"https:\/\/doi.org\/10.1142\/s0218126621500420","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,8,19]]}}}