{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,14]],"date-time":"2025-05-14T02:28:27Z","timestamp":1747189707884,"version":"3.40.5"},"reference-count":33,"publisher":"World Scientific Pub Co Pte Ltd","issue":"04","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2021,3,30]]},"abstract":"<jats:p>Today, field programmable gate array (FPGA) is becoming widely used as computational accelerators in many application domains such as image\/video processing, machine learning, and data mining. The inherent tolerance to the imprecise computation in such domains potentially provides an opportunity to trade quality of the results for higher energy efficiency. Therefore, this paper proposes a systematic methodology aiming to find the optimal energy saving corresponding to different quality bound, by approximating register-transfer level (RTL) designs on FPGA. As a case study, first, we investigate imprecise design on two submodules \u2014 adders and multipliers. By integrating the two combinational submodules with finite state machines (FSMs), several designs on a sequential circuit \u2014 color-to-grayscale converter \u2014 are further presented to offer a diverse range of energy consumption related to different quality constrains. Through this, we are able to set energy\u2013quality (E\u2013Q) parameters of our proposed methodology and configure the approximation knobs, capable of maximizing energy savings within different application-based quality margins. Experimental result demonstrates that leveraging E\u2013Q leads to an average [Formula: see text]\u2013[Formula: see text] savings in energy for modest loss in application output quality ([Formula: see text]), and [Formula: see text]\u2013[Formula: see text] energy savings for impact on relaxed quality constraints (3\u20137.5%).<\/jats:p>","DOI":"10.1142\/s0218126621500626","type":"journal-article","created":{"date-parts":[[2020,6,23]],"date-time":"2020-06-23T11:23:52Z","timestamp":1592911432000},"page":"2150062","source":"Crossref","is-referenced-by-count":0,"title":["Exploiting Energy\u2013Quality (E\u2013Q) Tradeoffs: A Case Study on Color-to-Grayscale Converters with Approximate Design on FPGA"],"prefix":"10.1142","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1236-6857","authenticated-orcid":false,"given":"Xiaokun","family":"Yang","sequence":"first","affiliation":[{"name":"Engineering Department, University of Houston Clear Lake, 2700 Bay Area Blvd, Houston, TX 77058, USA"}]},{"given":"Shi","family":"Sha","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Wilkes University, 84 West South Street, Wilkes-Barre, PA 18766, USA"}]}],"member":"219","published-online":{"date-parts":[[2020,8,27]]},"reference":[{"key":"S0218126621500626BIB001","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783710"},{"key":"S0218126621500626BIB002","doi-asserted-by":"publisher","DOI":"10.1145\/2934872.2934897"},{"key":"S0218126621500626BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2019.00075"},{"key":"S0218126621500626BIB004","first-page":"129","volume-title":"21st Int. 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