{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:37:18Z","timestamp":1740116238757,"version":"3.37.3"},"reference-count":23,"publisher":"World Scientific Pub Co Pte Ltd","issue":"08","funder":[{"DOI":"10.13039\/501100013101","name":"Scientific Research Plan Projects of Shaanxi Education Department","doi-asserted-by":"publisher","award":["20JY020"],"award-info":[{"award-number":["20JY020"]}],"id":[{"id":"10.13039\/501100013101","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["61904133"],"award-info":[{"award-number":["61904133"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61674118"],"award-info":[{"award-number":["61674118"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100010031","name":"Postdoctoral Research Foundation of China","doi-asserted-by":"publisher","award":["2018M640954"],"award-info":[{"award-number":["2018M640954"]}],"id":[{"id":"10.13039\/501100010031","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100012226","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100012226","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2021,6,30]]},"abstract":"<jats:p> This paper presents a 32-GS\/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the [Formula: see text] two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feedthrough, and signal feedthrough are presented. Inductor peaking technique is adopted to extend the bandwidth of the buffer between the first and the second stage. Based on the simulation results, the proposed FESC consumes 136[Formula: see text]mW at 32 GS\/s, and the signal-to-noise ratio (SNDR) is up to 39.55 dB at Nyquist input, achieving a state-of-the-art power efficiency. <\/jats:p>","DOI":"10.1142\/s0218126621501437","type":"journal-article","created":{"date-parts":[[2020,10,28]],"date-time":"2020-10-28T08:09:21Z","timestamp":1603872561000},"page":"2150143","source":"Crossref","is-referenced-by-count":1,"title":["A 32-GS\/s Front-End Sampling Circuit Achieving &gt;39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS"],"prefix":"10.1142","volume":"30","author":[{"given":"Lei","family":"Zhao","sequence":"first","affiliation":[{"name":"Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics Xidian University, Xi\u2019an 710071, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dengquan","family":"Li","sequence":"additional","affiliation":[{"name":"Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics Xidian University, Xi\u2019an 710071, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Henghui","family":"Mao","sequence":"additional","affiliation":[{"name":"Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics Xidian University, Xi\u2019an 710071, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ruixue","family":"Ding","sequence":"additional","affiliation":[{"name":"Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics Xidian University, Xi\u2019an 710071, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhangming","family":"Zhu","sequence":"additional","affiliation":[{"name":"Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics Xidian University, Xi\u2019an 710071, P.\u00a0R.\u00a0China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2020,11,20]]},"reference":[{"key":"S0218126621501437BIB001","first-page":"57","volume":"18","author":"Sun L.","year":"2020","journal-title":"ZTE Commun."},{"key":"S0218126621501437BIB002","first-page":"73","volume":"18","author":"Gao X.","year":"2020","journal-title":"ZTE Commun."},{"key":"S0218126621501437BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2713523"},{"key":"S0218126621501437BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2859757"},{"key":"S0218126621501437BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2828649"},{"key":"S0218126621501437BIB006","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2019.1570557"},{"key":"S0218126621501437BIB007","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126615500930"},{"key":"S0218126621501437BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2472642"},{"first-page":"60","volume-title":"2018 IEEE BiCMOS Compd. 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