{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:07:45Z","timestamp":1753884465420,"version":"3.41.2"},"reference-count":17,"publisher":"World Scientific Pub Co Pte Ltd","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2021,9,30]]},"abstract":"<jats:p> An ultra-wide bandwidth fully differential two-stage 65[Formula: see text]nm CMOS operational amplifier (Opamp) is presented, which uses a novel bandwidth extension technique called \u201cpole duplication\u201d. This technique is based on relocating the dominant pole with the same location with a non-dominant pole and adjusting 3-dB frequency and stability with a compensation network. Simulation results show that the proposed Opamp has 103[Formula: see text]MHz 3-dB bandwidth with a 2[Formula: see text]pF load capacitor. It consumes 9[Formula: see text]mA current from 1.2-V supply. Transition frequency of 2.4[Formula: see text]GHz and a gain of 29[Formula: see text]dB is accomplished. A 2[Formula: see text]pF load capacitance can be driven at a phase margin of [Formula: see text]. The suggested pole duplication technique is used to achieve higher 3-dB cut-off frequencies by adjusting the load capacitor. Fully differential two-stage Opamp is presented, which uses a novel bandwidth extension technique, is suitable for SoC active filter applications with 40[Formula: see text][Formula: see text]m layout area and ultra-wide 3-dB bandwidth. <\/jats:p>","DOI":"10.1142\/s0218126621502261","type":"journal-article","created":{"date-parts":[[2021,2,27]],"date-time":"2021-02-27T01:21:58Z","timestamp":1614388918000},"source":"Crossref","is-referenced-by-count":2,"title":["Ultra-Wide Bandwidth Fully Differential CMOS Opamp with a Novel Bandwidth Extension Technique for SoC Active Filter Applications"],"prefix":"10.1142","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0871-8677","authenticated-orcid":false,"given":"Toprak","family":"Kayansel\u00e7uk","sequence":"first","affiliation":[{"name":"T\u00dcB\u0130TAK-Informatics and Information Security Research Center, 41470 Gebze, Kocaeli, Turkey"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ertan","family":"Zencir","sequence":"additional","affiliation":[{"name":"T\u00dcB\u0130TAK-Informatics and Information Security Research Center, 41470 Gebze, Kocaeli, Turkey"},{"name":"Department of Electrical & Electronics Engineering, University of Turkish Aeronautical Association, 06790 Etimesgut, Ankara, Turkey"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2021,4,17]]},"reference":[{"volume-title":"Design of Analog CMOS Integrated Circuits","year":"2001","author":"Razavi B.","key":"S0218126621502261BIB001"},{"key":"S0218126621502261BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/ICEDSA.2010.5503080"},{"key":"S0218126621502261BIB003","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-014-0314-0"},{"key":"S0218126621502261BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/ECTICON.2009.5137067"},{"key":"S0218126621502261BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2008.4567260"},{"key":"S0218126621502261BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/ICECCT.2017.8117957"},{"key":"S0218126621502261BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2009.5012124"},{"key":"S0218126621502261BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2004.1356662"},{"key":"S0218126621502261BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2100270"},{"key":"S0218126621502261BIB010","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.858493"},{"key":"S0218126621502261BIB011","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2004.1399758"},{"volume-title":"Analysis and Design of Analog Integrated Circuits","year":"2001","author":"Gray P. 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