{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T18:42:33Z","timestamp":1761676953387,"version":"3.41.2"},"reference-count":63,"publisher":"World Scientific Pub Co Pte Ltd","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2021,9,30]]},"abstract":"<jats:p> The paper presents a low supply voltage CMOS voltage reference with low line sensitivity and high PSRR. Generally, the reference voltage is obtained using both complementary-to-absolute-temperature (CTAT) current and proportional-to-absolute-temperature (PTAT) current. This technique increases the complexity and area of the reference circuit. To overcome these drawbacks, the temperature compensated reference voltage has been proposed using only CTAT currents. Mostly, the CTAT current generators are simple, power-efficient, and area-efficient as compared to the PTAT current generators. The negative feedback loop has been formed in the proposed design to obtain a supply independent CTAT current and to avoid the use of startup drivers. The proposed circuit has been designed using Cadence virtuoso analog design environment in BSIM3V3 180[Formula: see text]nm CMOS technology. The simulation results of the proposed circuit show a reference voltage of 312[Formula: see text]mV with a temperature coefficient (TC) of 38.85[Formula: see text]ppm\/<jats:sup>\u2218<\/jats:sup>C over a wide temperature range of [Formula: see text]C to 125<jats:sup>\u2218<\/jats:sup>C with a supply voltage of 0.8[Formula: see text]V. The line sensitivity is 0.027% [Formula: see text] with a supply voltage ranging from 0.8[Formula: see text]V to 3[Formula: see text]V. The power supply rejection ratio (PSRR) without using any capacitive filter is observed as [Formula: see text] and [Formula: see text][Formula: see text]dB at 100[Formula: see text]Hz and 100[Formula: see text]kHz frequency, respectively. The circuit is simple and occupies a chip area of 0.0027[Formula: see text]mm<jats:sup>2<\/jats:sup>. <\/jats:p>","DOI":"10.1142\/s0218126621502273","type":"journal-article","created":{"date-parts":[[2021,2,27]],"date-time":"2021-02-27T01:21:58Z","timestamp":1614388918000},"source":"Crossref","is-referenced-by-count":7,"title":["A Low Supply Voltage, Low Line Sensitivity and High PSRR Subthreshold CMOS Voltage Reference"],"prefix":"10.1142","volume":"30","author":[{"given":"Arvind","family":"Thakur","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, Punjab, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1369-7073","authenticated-orcid":false,"given":"Rishikesh","family":"Pandey","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, Punjab, India"}]},{"given":"Shireesh Kumar","family":"Rai","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, Punjab, India"}]}],"member":"219","published-online":{"date-parts":[[2021,4,23]]},"reference":[{"key":"S0218126621502273BIB001","volume-title":"CMOS: Circuit Design, Layout, and Simulation","author":"Baker R. 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