{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T08:24:54Z","timestamp":1761294294521,"version":"3.41.2"},"reference-count":57,"publisher":"World Scientific Pub Co Pte Ltd","issue":"14","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2021,11]]},"abstract":"<jats:p> We propose a safety-oriented design process for IP-based safety-critical system-on-chip (SoC). The proposed safety process can facilitate the measurement of the robustness based on the safety-related metrics and scales of failure-induced risks in a system that can be employed to locate the critical components for protection to effectively diminish the influence of failures on the system. The risk reduction phase is activated to enhance the robustness of critical components identified by vulnerability analysis if the measured robustness is insufficient. An SoC-level safety design platform was built on the SystemC Synopsys Platform Architect MCO to demonstrate the core idea of the safety process. The safety-oriented design process for an ARM-embedded SoC modeled at the TLM level was conducted to demonstrate the feasibility of our safety approach. <\/jats:p>","DOI":"10.1142\/s0218126621502546","type":"journal-article","created":{"date-parts":[[2021,4,19]],"date-time":"2021-04-19T15:47:42Z","timestamp":1618847262000},"source":"Crossref","is-referenced-by-count":2,"title":["SoC-Level Safety-Oriented Design Process in Electronic System Level Development Environment"],"prefix":"10.1142","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0283-5960","authenticated-orcid":false,"given":"Kuen-Long","family":"Lu","sequence":"first","affiliation":[{"name":"College of Electrical Engineering and Computer Science, National Taipei University, 151, University Rd., San Shia District, New Taipei City 23741, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yung-Yuan","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Taipei University, 151, University Rd., San Shia District, New Taipei City 23741, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2021,5,19]]},"reference":[{"key":"S0218126621502546BIB001","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2004.14"},{"key":"S0218126621502546BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.69"},{"key":"S0218126621502546BIB003","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6993-4"},{"key":"S0218126621502546BIB004","doi-asserted-by":"publisher","DOI":"10.1016\/j.ress.2017.09.028"},{"key":"S0218126621502546BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2020.2993637"},{"key":"S0218126621502546BIB007","doi-asserted-by":"publisher","DOI":"10.1049\/cce:20000101"},{"key":"S0218126621502546BIB009","volume-title":"The Basics of FMEA","author":"Mikulak R. J.","year":"2008","edition":"2"},{"volume-title":"ESL Design and Verification: A Prescription for Electronic System Level Methodology","year":"2007","author":"Martin G.","key":"S0218126621502546BIB011"},{"key":"S0218126621502546BIB012","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2889665"},{"first-page":"416","volume-title":"Proc. Int. Conf. Dependable Systems and Networks (DSN)","author":"Kim S.","key":"S0218126621502546BIB013"},{"first-page":"61","volume-title":"Int. Conf. Dependable Systems and Networks","author":"Wang N.","key":"S0218126621502546BIB014"},{"first-page":"29","volume-title":"Proc. 36th Annual IEEE\/ACM Int. Symp. Microarchitecture (MICRO-36\u201903)","author":"Mukherjee S. S.","key":"S0218126621502546BIB015"},{"first-page":"243","volume-title":"25th IEEE VLSI Test Symp.","author":"Hosseinabady M.","key":"S0218126621502546BIB016"},{"first-page":"1","volume-title":"25th Norchip Conf.","author":"Tony S. M.","key":"S0218126621502546BIB017"},{"first-page":"492","volume-title":"Design, Automation and Test in Europe Conf. and Exhibition","author":"Mariani R.","key":"S0218126621502546BIB018"},{"first-page":"857","volume-title":"IEEE Int. Conf. Dependable Systems and Networks","author":"Ruiz J.-C.","key":"S0218126621502546BIB019"},{"key":"S0218126621502546BIB023","first-page":"1","volume-title":"1st REES Workshop","author":"Tabacaru B.-A.","year":"2015"},{"first-page":"1","volume-title":"2016 IFIP\/IEEE Int. Conf. Very Large Scale Integration (VLSI- SoC)","author":"Tabacaru B.","key":"S0218126621502546BIB024"},{"first-page":"364","volume-title":"2016 Euromicro Conf. Digital System Design (DSD)","author":"Tabacaru B.","key":"S0218126621502546BIB025"},{"first-page":"1","volume-title":"2016 Forum on Specification and Design Languages (FDL)","author":"Tabacaru B.","key":"S0218126621502546BIB026"},{"first-page":"180","volume-title":"IEEE 17th Int. Symp. Object\/Component\/Service-Oriented Real-Time Distributed Computing","author":"Ayestaran I.","key":"S0218126621502546BIB028"},{"first-page":"1","volume-title":"Proc. 2014 Forum on Specification and Design Languages (FDL)","author":"Ayestaran I.","key":"S0218126621502546BIB029"},{"key":"S0218126621502546BIB030","series-title":"Lecture Notes in Computer Science","first-page":"1","volume-title":"SAFECOMP 2014: Computer Safety, Reliability, and Security","volume":"8666","author":"Ayestaran I.","year":"2016"},{"first-page":"417","volume-title":"18th Asia and South Pacific Design Automation Conf. (ASP-DAC)","author":"Reiter S.","key":"S0218126621502546BIB031"},{"first-page":"534","volume-title":"2015 Euromicro Conf. Digital System Design","author":"Reiter S.","key":"S0218126621502546BIB032"},{"first-page":"62","volume-title":"2016 IEEE Int. High Level Design Validation and Test Workshop (HLDVT)","author":"Reiter S.","key":"S0218126621502546BIB033"},{"key":"S0218126621502546BIB034","first-page":"12","volume":"3","author":"Mollah A. H.","year":"2005","journal-title":"BioProcess Int."},{"first-page":"109","volume-title":"12th Int. Workshop on Intelligent Solutions in Embedded Systems (WISES)","author":"Weissnegger R.","key":"S0218126621502546BIB036"},{"key":"S0218126621502546BIB037","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2016.04.122"},{"key":"S0218126621502546BIB038","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-45480-1_29"},{"first-page":"1","volume-title":"Symp. Model-Driven Approaches for Simulation Engineering","author":"Weissnegger R.","key":"S0218126621502546BIB039"},{"key":"S0218126621502546BIB040","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2017.05.407"},{"first-page":"23","volume-title":"2017 IEEE Int. Conf. Software Testing, Verification and Validation (ICST)","author":"Jeong E.","key":"S0218126621502546BIB041"},{"key":"S0218126621502546BIB042","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-017-5702-9"},{"first-page":"123","volume-title":"2019 IFIP\/IEEE 27th Int. Conf. Very Large Scale Integration (VLSI-SoC)","author":"Bandeira V.","key":"S0218126621502546BIB043"},{"key":"S0218126621502546BIB044","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126617400096"},{"first-page":"26","volume-title":"2019 49th Annual IEEE\/IFIP Int. Conf. Dependable Systems and Networks (DSN)","author":"Chatzidimitriou A.","key":"S0218126621502546BIB046"},{"key":"S0218126621502546BIB047","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2020.113601"},{"first-page":"91","volume-title":"2016 IEEE Int. Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","author":"Iturbe X.","key":"S0218126621502546BIB048"},{"key":"S0218126621502546BIB049","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2651824"},{"first-page":"1","volume-title":"2020 23rd Int. Symp. Design and Diagnostics of Electronic Circuits & Systems (DDECS)","author":"Roux J.","key":"S0218126621502546BIB050"},{"key":"S0218126621502546BIB051","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2858773"},{"key":"S0218126621502546BIB052","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2939265"},{"first-page":"1","volume-title":"2020 IEEE 38th VLSI Test Symposium (VTS)","author":"da Silva F. A.","key":"S0218126621502546BIB053"},{"key":"S0218126621502546BIB054","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.70"},{"key":"S0218126621502546BIB055","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.06.020"},{"key":"S0218126621502546BIB056","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2013.09.002"},{"key":"S0218126621502546BIB057","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2880763"},{"key":"S0218126621502546BIB058","doi-asserted-by":"publisher","DOI":"10.5772\/38471"},{"key":"S0218126621502546BIB059","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2696538"},{"first-page":"354","volume-title":"8th Int. Symp. Advanced Intelligent Systems","author":"Chang K. J.","key":"S0218126621502546BIB060"},{"first-page":"680","volume-title":"7th Int. Conf. System Simulation and Scientific Computing","author":"Chen Y. Y.","key":"S0218126621502546BIB061"},{"key":"S0218126621502546BIB063","first-page":"15","volume-title":"IEEE Workshop Silicon Errors in Logic: System Effects (SELSE\u201909)","author":"Leveugle R.","year":"2009"},{"key":"S0218126621502546BIB064","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2010.2043540"},{"key":"S0218126621502546BIB065","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3010743"},{"key":"S0218126621502546BIB066","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.2020-0128"},{"key":"S0218126621502546BIB067","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3046075"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126621502546","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,16]],"date-time":"2021-12-16T13:59:32Z","timestamp":1639663172000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126621502546"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5,19]]},"references-count":57,"journal-issue":{"issue":"14","published-print":{"date-parts":[[2021,11]]}},"alternative-id":["10.1142\/S0218126621502546"],"URL":"https:\/\/doi.org\/10.1142\/s0218126621502546","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2021,5,19]]},"article-number":"2150254"}}