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The presented codes are constructed with the help of a computer and have two important features: first, they can correct single errors affecting one or two [Formula: see text]-bit bytes, and second, they use processor-friendly operations to encode\/decode data bits. The effectiveness of the presented codes is demonstrated on theoretical models of four-core and six-core processors. The obtained results show that the decoder throughput reaches 14.70[Formula: see text]Gbps, which is above the operating speed of 10G networks. Finally, the paper compares the proposed codes with BCH codes of similar properties. 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